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A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system 用于5G蜂窝系统的封装天线阵列的28GHz CMOS直接转换收发器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969019
H. Kim, Byoung-Sun Park, Seung-Min Oh, S. Song, Jong-Moon Kim, So-Hyeong Kim, Tak-Su Moon, Seung-Yeon Kim, Ji-Young Chang, Sung-Woong Kim, Woonsung Kang, Seung-Yoon Jung, Geum-Young Tak, Jincan Du, Yu-Suhk Suh, Y. Ho
{"title":"A 28GHz CMOS direct conversion transceiver with packaged antenna arrays for 5G cellular system","authors":"H. Kim, Byoung-Sun Park, Seung-Min Oh, S. Song, Jong-Moon Kim, So-Hyeong Kim, Tak-Su Moon, Seung-Yeon Kim, Ji-Young Chang, Sung-Woong Kim, Woonsung Kang, Seung-Yoon Jung, Geum-Young Tak, Jincan Du, Yu-Suhk Suh, Y. Ho","doi":"10.1109/RFIC.2017.7969019","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969019","url":null,"abstract":"This paper describes a 28GHz CMOS direct conversion transceiver with packaged 2×4 patch antenna arrays for 5G communication. Test results show good RF performances of Rx NF 6.7dB, Maximum Tx EIRP 31.5dBm (1PA Pout_sat =10.5dBm), LO integrated phase noise −37.8dBc (0.67°), Rx/Tx EVM around 2.2% (−33.1dB) at mid RF power, and well-fitted beam control capability.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122214527","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 108
A 42–46.4% PAE continuous class-F power amplifier with Cgd neutralization at 26–34 GHz in 65 nm CMOS for 5G applications 一种42-46.4% PAE的连续f类功率放大器，在26-34 GHz的65nm CMOS中进行Cgd中和，用于5G应用
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969055
Sheikh Nijam Ali, Pawan Agarwal, S. Mirabbasi, D. Heo
{"title":"A 42–46.4% PAE continuous class-F power amplifier with Cgd neutralization at 26–34 GHz in 65 nm CMOS for 5G applications","authors":"Sheikh Nijam Ali, Pawan Agarwal, S. Mirabbasi, D. Heo","doi":"10.1109/RFIC.2017.7969055","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969055","url":null,"abstract":"This paper presents a wideband high efficiency continuous class-F (CCF) power amplifier (PA) at mm-Wave frequencies for the first time. A tuned load with a high-order harmonic resonance network is used to shape the current and voltage waveforms for the proposed CCF CMOS PA. Further, a transformer with a tunable coupling-coefficient (ktune) is incorporated in the tuned load network to address the detrimental feedback effect caused by the increased transistor gate-drain capacitance (Cgd) in deep submicron CMOS technology. This technique allows precise neutralization of Cgd, reducing undesirable influence on the tuned load, and maximizing power-efficiency and stability. The CCF PA prototype, implemented in 65 nm CMOS exhibits more than 42% power added efficiency (PAE) over 8 GHz bandwidth (26–34 GHz), while delivering saturated output power (Psat) of 14.75 dBm at 30 GHz. This design presents one of the highest reported PAEs among mm-Wave CMOS PAs, achieving 46.4% peak PAE at 29 GHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128669894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
Peaking PA bias circuit for an APT CMOS Doherty PA APT CMOS Doherty PA的峰值PA偏置电路
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969099
Joonhoi Hur, P. Draxler, Jeong-won Park, Anthony Segoria, V. Aparin
{"title":"Peaking PA bias circuit for an APT CMOS Doherty PA","authors":"Joonhoi Hur, P. Draxler, Jeong-won Park, Anthony Segoria, V. Aparin","doi":"10.1109/RFIC.2017.7969099","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969099","url":null,"abstract":"This paper presents a peaking PA bias circuit for an Average Power Tracking (APT) CMOS Doherty PA, where the common supply voltage changes as the target average power changes. In order to have Doherty efficiency characteristics with APT, the peaking PA must have an adaptive bias circuit that shifts the bias as the supply voltage changes, activating the peaking PA at the correct backoff (6dB) from the Posat for that supply voltage. This bias circuit is demonstrated on a CMOS Doherty PA using standard 0.18um SOI. With the proposed bias circuit, the Doherty PA has specification compliant WCDMA performance (with DPD) up to 29dBm Pout, with 40–50% PAE (from 25–29dBm Pout) as the supply voltages ranges from 1.5V to 4V.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121839851","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 6–18 GHz GaN distributed power amplifier using reactive matching technique and simplified bias network 采用无功匹配技术和简化偏置网络的6-18 GHz GaN分布式功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969101
Hongjong Park, Sangho Lee, Kwang-Seon Choi, Jihoon Kim, Hyosung Nam, Jae-Duk Kim, Wangyong Lee, Changhoon Lee, Junghyun Kim, Y. Kwon
{"title":"A 6–18 GHz GaN distributed power amplifier using reactive matching technique and simplified bias network","authors":"Hongjong Park, Sangho Lee, Kwang-Seon Choi, Jihoon Kim, Hyosung Nam, Jae-Duk Kim, Wangyong Lee, Changhoon Lee, Junghyun Kim, Y. Kwon","doi":"10.1109/RFIC.2017.7969101","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969101","url":null,"abstract":"Two-stage reactively matched gain cells are applied to design a high-gain multi-octave distributed power amplifier (DPA) in this paper. The proposed reactively matched distributed amplifier (RMDA) structure shows a high gain and high output power performance within a small die size. The DC bias network of each section is simplified to implement the proposed structure in an MMIC and the design guide for the bias network is provided. A 6–18 GHz GaN DPA fabricated with the commercial 0.25-µm GaN HEMT process shows output power reaching 40.3–43.9 dBm with 16–27% PAE. To the best of our knowledge, this is the first demonstration of a GaN DPA using reactively matched gain cells, and it exhibits excellent small-signal gain and RF power performance capabilities among other reported GaN PAs with a multi-octave bandwidth up to the Ku-band.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":" 11","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120834891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
A fully-integrated SOI CMOS complex-impedance detector for matching network tuning in LTE power amplifier 用于LTE功率放大器匹配网络调谐的全集成SOI CMOS复杂阻抗检测器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969005
D. Nicolas, A. Serhan, A. Giry, T. Parra, E. Mercier
{"title":"A fully-integrated SOI CMOS complex-impedance detector for matching network tuning in LTE power amplifier","authors":"D. Nicolas, A. Serhan, A. Giry, T. Parra, E. Mercier","doi":"10.1109/RFIC.2017.7969005","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969005","url":null,"abstract":"This paper describes a wide dynamic-range and accurate complex-impedance detector for adaptive power amplifier load tuning systems. The detector IC, fabricated in a 130 nm SOI technology, consumes 7mA under 2.5V supply voltage. It can handle LTE signals with an input power from 0 dBm up to 40 dBm thanks to its variable attenuator system. System level measurements show that the detector has a very good accuracy in sensing the mismatched load impedance value in the VSWR region from 2∶1 to 6∶1.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115720997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator 带多环振荡器的低噪声无电感分数n次采样锁相环
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969029
Dongyi Liao, Rui-Xian Wang, F. Dai
{"title":"A low-noise inductor-less fractional-N sub-sampling PLL with multi-ring oscillator","authors":"Dongyi Liao, Rui-Xian Wang, F. Dai","doi":"10.1109/RFIC.2017.7969029","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969029","url":null,"abstract":"In this paper, a compact inductor-less PLL using multiple coupled rings oscillator is presented. Sub-sampling technique with soft loop gain switching is applied to reduce the in-band phase noise. As a result, the loop bandwidth can be widened, which suppresses the phase noise from ring oscillator as well. Fractional-N mode is implemented by utilizing the multiple phase outputs inherently generated by the ring VCO. Using multiple rings instead of one allows generating more phases for finer frequency resolution without decreasing oscillation frequency. The coupled multi-ring oscillator with proper phase shift also achieves reduced phase noise comparing to their single-ring counterpart. The PLL was implemented in a 0.13um CMOS technology, consuming 19 mW from a 1.3 V power supply. The measured largest in-band fractional spur at 2.08 MHz is −42 dBc. The measured integrated jitters were 571 fs and 690 fs around 1.2GHz output in integer mode and fractional mode respectively, achieving a FoM of −230 dB.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121308619","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Bi-directional flip-chip 28 GHz phased-array core-chip in 45nm CMOS SOI for high-efficiency high-linearity 5G systems 45纳米CMOS SOI双向倒装28 GHz相控阵核心芯片，用于高效高线性5G系统
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969017
Umut Kodak, Gabriel M. Rebeiz
{"title":"Bi-directional flip-chip 28 GHz phased-array core-chip in 45nm CMOS SOI for high-efficiency high-linearity 5G systems","authors":"Umut Kodak, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2017.7969017","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969017","url":null,"abstract":"This paper presents a 0 mW two-channel 28 GHz bi-directional phased-array chip packaged using flip-chip interconnects in 45nm CMOS SOI. The design alternates switched-LC phase shifters with switched attenuators to result in 5-bit phase control with an rms gain and phase error <0.8 dB and 5°, respectively at 25–33 GHz. In the RX mode, the measured gain is −10 dB and the NF is 10 dB with an input P1dB of 5 dBm. In the TX mode, the measured output P1dB is −2 dBm. This work presents an efficient solution for the construction of high-linearity and high-power phased-array base-stations by combining GaAs front-ends with a passive silicon core chip.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"102 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130794625","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
An X-band inverse class-F SiGe HBT cascode power amplifier With harmonic-tuned output transformer 带谐波调谐输出变压器的x波段反f类SiGe HBT级联码功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969100
Inchan Ju, J. Cressler
{"title":"An X-band inverse class-F SiGe HBT cascode power amplifier With harmonic-tuned output transformer","authors":"Inchan Ju, J. Cressler","doi":"10.1109/RFIC.2017.7969100","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969100","url":null,"abstract":"This paper presents a highly efficient X-band inverse class-F SiGe HBT cascode power amplifier (PA) to overcome performance limitations imposed by device breakdown. Simultaneous fundamental and 2nd/3rd harmonic matching is achieved using an output transformer with an embedded capacitor at its center-tap, which enables inverse class-F operation. Use of a cascode topology with a low base impedance termination and minimum voltage-current waveform overlap extends the VCE swing on the upper SiGe HBT in the cascode to beyond BVCBO, boosting output power and power added efficiency (PAE). As proof of concept, the inverse class-F PA was implemented in 0.13-µm SiGe BiCMOS technology. Measured results show an output power of 25.8 dBm and 51.1% peak PAE at 10 GHz, when operated on a 3.0 V supply. To the authors' best knowledge, our work has the highest efficiency among all Si-based X-band PAs with comparable output power.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121225729","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Highly-miniaturized 2-channel mm-wave radar sensor with on-chip folded dipole antennas 带有片上折叠偶极子天线的高度小型化2通道毫米波雷达传感器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969094
H. Ng, W. Ahmad, M. Kucharski, Jeng-Hau Lu, D. Kissinger
{"title":"Highly-miniaturized 2-channel mm-wave radar sensor with on-chip folded dipole antennas","authors":"H. Ng, W. Ahmad, M. Kucharski, Jeng-Hau Lu, D. Kissinger","doi":"10.1109/RFIC.2017.7969094","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969094","url":null,"abstract":"This paper describes a miniaturized 2-channel system-on-chip radar sensor in a SiGe BiCMOS technology. It includes on-chip folded dipole antennas that utilize a localized backside etching technique with a novel selective etching approach that is able to improve the radiation efficiency and the mechanical stability of the chip. The transceiver is equipped with a 30-GHz VCO that is complemented with a frequency quadrupler to generate a 120-GHz carrier signal. The 2 transmit channels can be combined to increase the effective isotropic radiated power by 6 dB and to implement a SIMO radar. The transceiver also includes BPSK modulators as well as I/Q receivers and can be utilized to build a flexible MIMO radar using frequency-modulated continuous-wave with time and delta-sigma modulator-based frequency division multiplexing as well as pseudo-random noise radar techniques. Radar measurement using digital-beamforming method with 10-GHz modulation bandwidth was performed to show the applicabilty of the proposed system.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121434235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 0.3 GHz to 1.4 GHz N-path mixer-based code-domain RX with TX self-interference rejection 一种基于0.3 GHz至1.4 GHz n路混频器的码域RX，具有TX自干扰抑制功能
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969070
Abhishek Agrawal, A. Natarajan
{"title":"A 0.3 GHz to 1.4 GHz N-path mixer-based code-domain RX with TX self-interference rejection","authors":"Abhishek Agrawal, A. Natarajan","doi":"10.1109/RFIC.2017.7969070","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969070","url":null,"abstract":"A code-domain N-path RX is proposed based on PN-code modulated LO pulses for concurrent reception of two code-modulated signals. Additionally, a combination of Walsh-Function and PN sequence is proposed to translate in-band TX self-interference (SI) to out-of-band at N-path RX output enabling frequency filtering for high SI rejection. A 0.3 GHz–1.4 GHz 65-nm CMOS implementation has 35 dB gain for desired signals and concurrently receives two RX signals while rejecting mismatched spreading codes at RF input. Proposed TX SI mitigation approach results in 38.5 dB rejection for −11.8dBm 1.46 Mb/s QPSK modulated SI at RX input. The RX achieves 23.7dBm OP1dB for in-band SI, while consuming ∼35mW and occupies 0.31mm2.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128761587","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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