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2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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Joint TX and feedback RX IQ mismatch compensation for integrated direct conversion transmitters 集成直接转换发射机的联合TX和反馈RX IQ失配补偿
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969015
H. Choo, C. Sestok, Xiaoxi Zhang, N. Klemmer
{"title":"Joint TX and feedback RX IQ mismatch compensation for integrated direct conversion transmitters","authors":"H. Choo, C. Sestok, Xiaoxi Zhang, N. Klemmer","doi":"10.1109/RFIC.2017.7969015","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969015","url":null,"abstract":"The direct conversion (DC) architecture has been adopted for wireless base-station transceivers due to its cost and area efficiency. The shortcomings of DC transceivers need to be overcome to meet their high performance requirements. In-phase (I) and quadrature phase (Q) mismatch is one of most significant impairments. This paper presents an integrated, on-line mismatch compensation system which calibrates frequency-dependent transmitter (TX) and feedback receiver (FBRX) IQ mismatches using the digital TX signal as a reference. The proposed method was fabricated in 45nm CMOS technology. Measurements show 60 dBc TX ACPR for 20MHz LTE low-IF signals. TX EVM of 0.8% is achieved with 20MHz zero-IF LTE signals.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123042025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah in 65nm CMOS 完全集成的可重构低功耗Sub-GHz收发器，用于65nm CMOS的802.11ah
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969062
Meng Wei, Zheng Song, Peiyi Li, Jianfu Lin, Junfeng Zhang, Jiachen Hao, B. Chi
{"title":"A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah in 65nm CMOS","authors":"Meng Wei, Zheng Song, Peiyi Li, Jianfu Lin, Junfeng Zhang, Jiachen Hao, B. Chi","doi":"10.1109/RFIC.2017.7969062","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969062","url":null,"abstract":"A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah is presented. The receiver uses the low-IF/zero-IF reconfigurable architecture to support 1, 2 and 8MHz signal bandwidth, and the needed number of the Op-Amps in the analog baseband is reduced to 3 while providing 4th-order channel filtering and programmable gain amplification. The transmitter uses the digital polar architecture, with the open-loop phase modulator to support wide signal bandwidth and the inverse Class-D digital power amplifier to enhance the power efficiency. A Class-C VCO with dynamic gate bias technique for robust start-up and AFC-assisted oscillation amplitude control technique is used in the fractional-N PLL frequency synthesizer. The transceiver has been implemented in 65nm CMOS. The measured results show that the receiver achieves <3.89dB NF and 47dB image rejection, and the frequency synthesizer achieves −127.8dBc/Hz phase noise at 1MHz offset and −94.6dBc/Hz in-band phase noise from a 1.536GHz carrier. The transmitter demonstrates 6.98% EVM for 900MHz pi/4-DQPSK signals at 6.3 dBm output power without pre-distortion. The receiver and the frequency synthesizer consume 6.4mA and 5.5mA current from a 1.2V power supply, respectively, and the DPA in the transmitter achieves 51.7% drain efficiency at 17.1dBm peak output power.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"590 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123186292","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Waveform engineering in a mm-Wave stacked-HBT switching power amplifier 毫米波叠置hbt开关功率放大器的波形工程
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969056
K. Datta, H. Hashemi
{"title":"Waveform engineering in a mm-Wave stacked-HBT switching power amplifier","authors":"K. Datta, H. Hashemi","doi":"10.1109/RFIC.2017.7969056","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969056","url":null,"abstract":"A new family of hybrid stacked power amplifiers (named as ‘Class-K’) are presented where each of the series stacked transistors can operate independently as different class of switching amplifiers. The voltage and current waveforms of the stacked transistors are shaped by independent harmonic load networks connected to the collector nodes of each of the stacked HBTs. A properly-designed Class-K amplifier can simultaneously achieve the high efficiency of Class-E/F amplifiers, high output power of Class-EF amplifiers, and high power gain of Class-E amplifiers. A proof-of-concept two-stage two-stacked balanced Class-K amplifier implemented in a 0.18 µm SiGe HBT BiCMOS process demonstrates 25.5 dBm output power and 26% peak PAE at 34 GHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126820282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Linear CMOS power amplifier at Ka-band with ultra-wide video bandwidth 具有超宽视频带宽的ka波段线性CMOS功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969057
Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, J. Son, Bumman Kim
{"title":"Linear CMOS power amplifier at Ka-band with ultra-wide video bandwidth","authors":"Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, J. Son, Bumman Kim","doi":"10.1109/RFIC.2017.7969057","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969057","url":null,"abstract":"A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental nonlinear mixing. The PA, composed of 3 cascaded common-source (CS) stages, achieves peak PAE of 21.8% at output power of 14 dBm with 22 dB gain. The 3rd order inter-modulation distortion (IMD3) at an output power of 5 dBm is under −30 dBc for a video bandwidth of 1 GHz. The PA and LDO are fabricated in a 65 nm CMOS process and occupy 0.53 mm2.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124435183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 3.4Mbps NFC card emulator supporting 40mm2 loop antenna 3.4Mbps NFC卡仿真器，支持40mm2环形天线
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969063
Tieng Ying Choke, Y. Tan, C. Leow, Junmin Cao, Liming Jin, Huajiang Zhang, Hon Cheong Hor, E. Low, W. Shu, O. Shana'a
{"title":"A 3.4Mbps NFC card emulator supporting 40mm2 loop antenna","authors":"Tieng Ying Choke, Y. Tan, C. Leow, Junmin Cao, Liming Jin, Huajiang Zhang, Hon Cheong Hor, E. Low, W. Shu, O. Shana'a","doi":"10.1109/RFIC.2017.7969063","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969063","url":null,"abstract":"For compact integration of 13.56MHz NFC functionality in mobile devices, a small planar loop antenna is a necessity. Active load modulation (ALM) is a commonly adopted technique to boost load modulation amplitude to overcome weak inductive coupling in small antennas. However, due to the challenges of phase synchronization, ALM is mainly limited to low data rate NFC applications. This paper describes the challenges of supporting NFC Very High Bit Rate (VHBR) Card Emulation Mode (PICC) in small antennas. An ultra-fast retimed phase synchronization PLL technique is proposed to overcome the technical challenges of ALM for high data rate uplink transmission. A sub-sampling ADC topology is implemented as VHBR ASK envelope demodulator. A clock extractor-based PLL provides precise synchronized continuous clock to the high speed sub-sampling ADC for accurate demodulation of all ASK envelopes with modulation index (MI) ranging from 8% to 100%.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"43 4-7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132937129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A wideband linear direct digital RF modulator using harmonic rejection and I/Q-interleaving RF DACs 采用谐波抑制和I/ q交错射频dac的宽带线性直接数字射频调制器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969049
M. Mehrpoo, M. Hashemi, Y. Shen, R. van Leuken, M. Alavi, L. D. de Vreede
{"title":"A wideband linear direct digital RF modulator using harmonic rejection and I/Q-interleaving RF DACs","authors":"M. Mehrpoo, M. Hashemi, Y. Shen, R. van Leuken, M. Alavi, L. D. de Vreede","doi":"10.1109/RFIC.2017.7969049","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969049","url":null,"abstract":"This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2<sup>nd</sup>-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2×9-bit DDRM core occupies 0.21mm<sup>2</sup> and consumes only 110mW at 1 GHz. Within the 0.9–3.1GHz frequency range, the peak output power reaches +9.2dBm and the 3<sup>rd</sup>/5<sup>th</sup> harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, −44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than −30 dB and −45 dB, respectively, and ACPR remains as low as −44 dBc up to a wide bandwidth of 110 MHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129532095","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A dual core power combining digital power amplifier for 802.11b/g/n with +26.8dBm linear output power in 28nm CMOS 802.11b/g/n双核心组合数字功率放大器，线性输出功率+26.8dBm，采用28nm CMOS
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969050
A. Wong, P. Godoy, O. Carnu, Hao Li, Xingliang Zhao, A. Olyaei, A. Ghaffari, S. Tam, R. Winoto, Randy Tsang
{"title":"A dual core power combining digital power amplifier for 802.11b/g/n with +26.8dBm linear output power in 28nm CMOS","authors":"A. Wong, P. Godoy, O. Carnu, Hao Li, Xingliang Zhao, A. Olyaei, A. Ghaffari, S. Tam, R. Winoto, Randy Tsang","doi":"10.1109/RFIC.2017.7969050","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969050","url":null,"abstract":"This paper presents a digital power amplifier with two cores that are power combined for a Psat of +32.5dBm. Assisted by an on-chip digital pre-distortion, a transmitted output power of +26.8dBm for 802.11g 54 Mbps 64-QAM is achieved. This is the highest reported linear output power for a digital power amplifier designed for 802.11b/g/n applications in bulk 28nm CMOS. A total area of 0.36mm2 is used for the power amplifier cores and combiner. Drawing off of a 3.3V supply, this power amplifier has a drain efficiency of 21.2% at the maximum linear output power.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127602109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A 16-element 4-beam 1GHz-IF 100MHz-bandwidth Interleaved Bit-Stream digital beamformer in 40nm CMOS 一种16元4波束1GHz-IF 100mhz带宽的40nm CMOS交错比特流数字波束形成器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969033
Sunmin Jang, J. Jeong, Rundao Lu, M. Flynn
{"title":"A 16-element 4-beam 1GHz-IF 100MHz-bandwidth Interleaved Bit-Stream digital beamformer in 40nm CMOS","authors":"Sunmin Jang, J. Jeong, Rundao Lu, M. Flynn","doi":"10.1109/RFIC.2017.7969033","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969033","url":null,"abstract":"This paper introduces a 16 element, 1GHz IF input, digital beamformer (DBF) that generates 4 independent simultaneous beams, with 100MHz bandwidth. Although DBF has several advantages over analog beamforming, including higher accuracy and multiple beam generation, application of on-chip DBF has been limited due to high power consumption and large die area. The proposed architecture addresses these issues by combining efficient Continuous-Time Band-Pass Delta Sigma Modulators (CTBPDSMs) with Interleaved Bit-Stream Processing (IL-BSP). IL-BSP saves 80% power and 80% area compared to a conventional DSP approach. The overall 16 element array has a measured 58.5dB SNDR and a 59.6dB SNR over a 100MHz bandwidth (11.2dB array gain). Thanks to the IL-BSP approach, the measured beam patterns are near ideal.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114291913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A CMOS UWB receiver with reconfigurable notch filters for narrow-band interferers 一种具有可重构陷波滤波器的CMOS超宽带接收机，用于窄带干扰
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969091
Paria Sepidband, K. Entesari
{"title":"A CMOS UWB receiver with reconfigurable notch filters for narrow-band interferers","authors":"Paria Sepidband, K. Entesari","doi":"10.1109/RFIC.2017.7969091","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969091","url":null,"abstract":"In this paper, an interferer-tolerant receiver for the first group of ultra-wideband systems (3.1–4.8 GHz) is presented. The entire system operates in two modes; detecting and receiving. In the detecting mode, the locations of up to three blockers in 2.35–2.75 GHz and 5.1–5.9 GHz bands are reported to three notch filters used in the receiving path for rejection. In the receiving mode, the receiver operates normally with the activated notch filters. The entire system is integrated in a standard TSMC CMOS 65-nm technology and consumes up to 23.8 mW and 9.6 mW, in the receiving and detecting modes, respectively, with a 1 V voltage supply. The receiver can achieve an out-of-band IIP3 of as high as 18.9 dBm.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130557684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 77-GHz active millimeter-wave reflector for FMCW radar 用于FMCW雷达的77 ghz有源毫米波反射器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI: 10.1109/RFIC.2017.7969080
M. S. Dadash, J. Hasch, S. Voinigescu
{"title":"A 77-GHz active millimeter-wave reflector for FMCW radar","authors":"M. S. Dadash, J. Hasch, S. Voinigescu","doi":"10.1109/RFIC.2017.7969080","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969080","url":null,"abstract":"An 18-mW active millimeter-wave reflector fabricated in 45-nm SOI CMOS technology exhibits a peak gain of 20 dB at 77 GHz, a 3-dB bandwidth of 5 GHz from 75.5 to 80.5 GHz, and a 50-Ω noise figure of 7.5–8.5 dB over the same frequency band. It consists of an LNA, a BPSK modulator and two variable gain output stages each driving a separate transmit antenna. The chip occupies 570µm×880µm and is flip-chip mounted on a 7mm×7mm flexible interposer with two transmit and one receive antenna.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121551874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
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