A dual core power combining digital power amplifier for 802.11b/g/n with +26.8dBm linear output power in 28nm CMOS

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-01 DOI:10.1109/RFIC.2017.7969050

A. Wong, P. Godoy, O. Carnu, Hao Li, Xingliang Zhao, A. Olyaei, A. Ghaffari, S. Tam, R. Winoto, Randy Tsang

引用次数: 2

Abstract

This paper presents a digital power amplifier with two cores that are power combined for a Psat of +32.5dBm. Assisted by an on-chip digital pre-distortion, a transmitted output power of +26.8dBm for 802.11g 54 Mbps 64-QAM is achieved. This is the highest reported linear output power for a digital power amplifier designed for 802.11b/g/n applications in bulk 28nm CMOS. A total area of 0.36mm2 is used for the power amplifier cores and combiner. Drawing off of a 3.3V supply, this power amplifier has a drain efficiency of 21.2% at the maximum linear output power.

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802.11b/g/n双核心组合数字功率放大器，线性输出功率+26.8dBm，采用28nm CMOS

本文提出了一种双核数字功率放大器，用于+32.5dBm的Psat。在片上数字预失真的辅助下，802.11g 54 Mbps 64-QAM的传输输出功率为+26.8dBm。这是为批量28nm CMOS 802.11b/g/n应用而设计的数字功率放大器的最高线性输出功率。总面积为0.36mm2用于功率放大器核心和组合器。利用3.3V电源，该功率放大器在最大线性输出功率下的漏极效率为21.2%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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