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2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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A 4mW-RX 7mW-TX IEEE 802.11ah fully-integrated RF transceiver 4mW-RX 7mW-TX IEEE 802.11ah全集成射频收发器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-07-05 DOI: 10.1109/RFIC.2017.7969060
A. Ba, K. Salimi, Paul Mateman, Pepijn Boer, J. V. D. van den Heuvel, Jordy Gloudemans, J. Dijkhuis, M. Ding, Yao-Hong Liu, Christian Bachmann, G. Dolmans, K. Philips
{"title":"A 4mW-RX 7mW-TX IEEE 802.11ah fully-integrated RF transceiver","authors":"A. Ba, K. Salimi, Paul Mateman, Pepijn Boer, J. V. D. van den Heuvel, Jordy Gloudemans, J. Dijkhuis, M. Ding, Yao-Hong Liu, Christian Bachmann, G. Dolmans, K. Philips","doi":"10.1109/RFIC.2017.7969060","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969060","url":null,"abstract":"An IEEE 802.11ah-compliant RF transceiver with a direct-conversion receiver and a fully-digital polar transmitter is presented. For the receiver, a current-mode RF front-end covers the mandatory modes worldwide from 755MHz to 928MHz. The digitally-assisted analog baseband achieves variable gains and bandwidths with an automatic gain/DC-offset calibration. Implemented in 40nm CMOS with 1V supply, this receiver achieves −104dBm sensitivity in the 1MHz MCS0 mode (i.e., 300kbp/s). It fulfils the adjacent channel rejection requirements with at least 17dB margin. The digital polar transmitter achieves −31dB EVM and 10dB spectral mask margin.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115978217","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
A 2.4GHz BLE-compliant fully-integrated wakeup receiver for latency-critical IoT applications using a 2-dimensional wakeup pattern in 90nm CMOS 2.4GHz ble兼容全集成唤醒接收器，适用于延迟关键型物联网应用，采用90nm CMOS二维唤醒模式
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-07-05 DOI: 10.1109/RFIC.2017.7969044
M. Ding, Peng Zhang, Chuang Lu, Yan Zhang, Stefano Traferro, G. van Schaik, Yao-Hong Liu, J. Huijts, Christian Bachmann, G. Dolmans, K. Philips
{"title":"A 2.4GHz BLE-compliant fully-integrated wakeup receiver for latency-critical IoT applications using a 2-dimensional wakeup pattern in 90nm CMOS","authors":"M. Ding, Peng Zhang, Chuang Lu, Yan Zhang, Stefano Traferro, G. van Schaik, Yao-Hong Liu, J. Huijts, Christian Bachmann, G. Dolmans, K. Philips","doi":"10.1109/RFIC.2017.7969044","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969044","url":null,"abstract":"This paper presents a wakeup receiver for latency-critical IoT applications in 90nm CMOS, which is fully compliant to many popular IoT wireless standards with constant envelope modulations, such as Bluetooth Low Energy and IEEE802.15.4. Paired with a standard-compliant transmitter, the proposed wakeup receiver method minimizes the overhead in system power, area and complexity. The proposed 2-dimensional wakeup pattern reduces the latency of a wakeup event to below 100µs. Supplied at a battery voltage of 2V, the chip fully integrates a power management unit, a wakeup receiver with offset and noise suppression, a low power digital baseband with automatic gain control and RSSI estimation, and a crystal oscillator. With a BLE compliant signal, the chip achieves −58dBm sensitivity, and a >600s mean time without false alarm, consuming 195µA.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-07-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124357393","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology 在65nm CMOS技术中，具有高效率的功率回退的20dBm反相级epa
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-06 DOI: 10.1109/RFIC.2017.7969087
A. Ghahremani, A. Annema, B. Nauta
{"title":"A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology","authors":"A. Ghahremani, A. Annema, B. Nauta","doi":"10.1109/RFIC.2017.7969087","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969087","url":null,"abstract":"This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A digitally-tuned triple-band transformer power combiner for CMOS power amplifiers 用于CMOS功率放大器的数字调谐三频带变压器功率合成器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969085
Rahul Singh, J. Paramesh
{"title":"A digitally-tuned triple-band transformer power combiner for CMOS power amplifiers","authors":"Rahul Singh, J. Paramesh","doi":"10.1109/RFIC.2017.7969085","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969085","url":null,"abstract":"This paper presents the design and implementation of a CMOS transformer combiner that can be reconfigured to have similar efficiencies at widely separated frequency bands. Conventional transformer combiners employ a fixed tuning capacitance in the secondary network to optimize the efficiency for single frequency standard. In this work, we present a modified transformer combiner where digitally-switchable capacitors introduced at low-swing nodes within the combiner network enable frequency reconfiguration using CMOS switches. A 65 nm CMOS triple-band (2.5/3/3.5 GHz) power amplifier (PA) chip employing the reconfigurable combiner is also presented.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"46 41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116744075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 32 GHz 20 dBm-PSAT transformer-based Doherty power amplifier for multi-Gb/s 5G applications in 28 nm bulk CMOS 基于32ghz 20dbm - psat变压器的Doherty功率放大器，用于28nm块状CMOS中多gb /s 5G应用
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969013
P. Indirayanti, P. Reynaert
{"title":"A 32 GHz 20 dBm-PSAT transformer-based Doherty power amplifier for multi-Gb/s 5G applications in 28 nm bulk CMOS","authors":"P. Indirayanti, P. Reynaert","doi":"10.1109/RFIC.2017.7969013","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969013","url":null,"abstract":"This paper presents a 32 GHz transformer-based Doherty power amplifier (PA) in a 28 nm bulk CMOS process. There are two techniques proposed: linearization by means of AM-PM and AM-AM compensation of the class AB and the class C amplifiers; and parallel-series-parallel power power combiner, wherein a current-mode parallel combiner complements the Doherty's voltage-mode series combiner to boost the output power. A saturated output power (PSAT ) of 19.8 dBm and an OP1dB of 16 dBm are accomplished from 1V supply while supporting 15 Gb/s 64-QAM amplification at 11.7 dBm average output power. The chip achieves 21% PAE at PSAT and occupies 0.59 mm2 active area.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114853439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
An ultra low-cost 32-element 28 GHz phased-array transceiver with 41 dBm EIRP and 1.0–1.6 Gbps 16-QAM link at 300 meters 一个超低成本的32元28 GHz相控阵收发器，EIRP为41 dBm, 300米距离16-QAM链路为1.0-1.6 Gbps
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969020
K. Kibaroglu, M. Sayginer, Gabriel M. Rebeiz
{"title":"An ultra low-cost 32-element 28 GHz phased-array transceiver with 41 dBm EIRP and 1.0–1.6 Gbps 16-QAM link at 300 meters","authors":"K. Kibaroglu, M. Sayginer, Gabriel M. Rebeiz","doi":"10.1109/RFIC.2017.7969020","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969020","url":null,"abstract":"This paper presents a 32-element phased-array architecture suitable for fifth-generation (5G) communication links. A 28–32 GHz silicon core chip is designed with 4 transmit/receive elements each with 14 dB gain control, 6-bit phase control, 4.6 dB measured noise figure (NF) in the RX mode and 10 dBm output 1 dB compression point (OP1dB) in the TX mode. Eight of these chips are flipped on a low-cost printed circuit board (PCB) with integrated antennas and Wilkinson combiners. The 32-element array has a measured EIRP of 41 dBm at P1dB, can scan to ±20° and ±50° in E- and H-planes, and comsumes 4.2 W and 6.4 W in RX and TX modes, respectively. The array is used in a 300 meter wireless link and achieves a data rate of 1.0–1.6 Gbps at 16-QAM for all scan angles with <12% EVM. To our knowledge, this represents state-of-the art in 28 GHz phased-arrays in terms of chip performance and integration level.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130046409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 63
A full-duplex receiver with 80MHz bandwidth self-interference cancellation circuit using baseband Hilbert transform equalization 采用基带希尔伯特变换均衡的80MHz带宽全双工接收机自干扰消除电路
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969092
A. El Sayed, A. Ahmed, A. K. Mishra, A. H. M. Shirazi, Sang-Pil Woo, Y.S. Choi, S. Mirabbasi, S. Shekhar
{"title":"A full-duplex receiver with 80MHz bandwidth self-interference cancellation circuit using baseband Hilbert transform equalization","authors":"A. El Sayed, A. Ahmed, A. K. Mishra, A. H. M. Shirazi, Sang-Pil Woo, Y.S. Choi, S. Mirabbasi, S. Shekhar","doi":"10.1109/RFIC.2017.7969092","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969092","url":null,"abstract":"To enable simultaneous full-duplex radios, self-interference (SI) cancellation (SIC) circuits that attain large cancellation bandwidths (BWs) are needed to support modern standards such as Long-Term Evolution (LTE). For mobile applications, SIC should be linear, tunable, fully monolithic (compact form factor) and must be implemented at the radio-frequency (RF) front-end. Emulating the group delay (GD) and complex impedance of the SI channel, an SIC circuit is proposed that achieves an 80 MHz of SIC BW using just a single tap delay. GD is estimated using frequency translations and baseband (BB) low pass filtering, and complex impedance is emulated using a vector modulator (VM). We prove that the combination of GD and VM results in a time-domain Hilbert transform equalization (HTE), enabling broadband cancellation and reducing the number of GD taps needed, thereby saving area. Implementing HTE at BB using passive circuits further reduces area, power consumption and maintains linearity. A prototype in 0.13-µm CMOS process occupies 0.4 mm2 and attains 23 dB of SIC measured over an 80-MHz signal BW, while consuming 13 mW. Total power and area including the receiver is 64.4 mW and 0.72mm2, respectively.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121287865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Adaptive Gain and Phase Adjustment for local linearization of Power Amplifiers of micro/mm-wave Phase arrays 微/毫米波相阵功率放大器局部线性化的自适应增益和相位调整
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969058
Farid Shirinfar, R. Rofougaran, S. Pamarti
{"title":"Adaptive Gain and Phase Adjustment for local linearization of Power Amplifiers of micro/mm-wave Phase arrays","authors":"Farid Shirinfar, R. Rofougaran, S. Pamarti","doi":"10.1109/RFIC.2017.7969058","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969058","url":null,"abstract":"A wideband, local Power Amplifier (PA) linearization technique is presented. The proposed Adaptive Gain and Phase Adjustment (AGPA) local linearization technique compensates for both AM-AM and AM-PM distortion of PA for large channel bandwidths of hundreds of megahertz. A 60GHz PA designed in a 28nm CMOS process is designed and measured. AGPA improves the OP1dB of the stacked PA by 2.8dB from 9.5dBm to 12.3dBm and reduces the IM3 products by 3dB with a tone spacing of 200MHz at 8dBm output power.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048982","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A 64 µW, 23 dB gain, 8 dB NF, 2.4 GHz RF front-end for ultra-low power Internet-of-Things transceivers 64µW, 23 dB增益，8 dB NF, 2.4 GHz射频前端，用于超低功耗物联网收发器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969048
Anjana Dissanayake, Hyun-Gi Seok, Oh-Yong Jung, Sok-Kyun Han, Sang-Gug Lee
{"title":"A 64 µW, 23 dB gain, 8 dB NF, 2.4 GHz RF front-end for ultra-low power Internet-of-Things transceivers","authors":"Anjana Dissanayake, Hyun-Gi Seok, Oh-Yong Jung, Sok-Kyun Han, Sang-Gug Lee","doi":"10.1109/RFIC.2017.7969048","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969048","url":null,"abstract":"An ultra-low power (ULP) 2.4 GHz RF front-end which consists of a low noise amplifier (LNA) and a passive mixer in a standard 65nm CMOS is presented. LNA adopts a complementary input stage and a current reused 2nd gain stage to achieve a high gain under a low power dissipation with an added linearization method. RF Down-conversion is implemented with a highly linearized complementary passive mixer, which adopts transmission gate type switches. With fully on-chip components, the front-end achieves 23 dB conversion gain, 8 dB NF, −36 dBm P1dB and −21 dBm IIP3 while dissipating a 64 µW power from a 0.6 V supply voltage. LNA achieves a high voltage gain of 26.3 dB and minimum NF of 5.5 dB with a P1dB of −27 dBm and IIP3 of −13 dBm.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114188445","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A 2×2 802.11ac WiFi transceiver supporting per channel 160MHz operation in 28nm CMOS 一个2×2 802.11ac WiFi收发器，支持每通道160MHz的28nm CMOS操作
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969052
Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, W. Chang, Chang-Ming Lai, T. Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, W. Hsu, J. Zhan
{"title":"A 2×2 802.11ac WiFi transceiver supporting per channel 160MHz operation in 28nm CMOS","authors":"Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, W. Chang, Chang-Ming Lai, T. Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, W. Hsu, J. Zhan","doi":"10.1109/RFIC.2017.7969052","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969052","url":null,"abstract":"This paper presents a dual-band 2×2 WiFi transceiver in 28nm bulk CMOS. Achieved receiver and transmitter EVM floor at 5GHz for 160MHz per channel are −35dB and −33dB, respectively. The 2.4GHz integrated PA provides 26.5dBm saturated output power while its 5GHz counterpart delivers 26dBm. The 2.4GHz receiver features mixer first architecture while the transmitter includes a 2nd harmonic notch for emission control.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116660691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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