A 2×2 802.11ac WiFi transceiver supporting per channel 160MHz operation in 28nm CMOS

Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, W. Chang, Chang-Ming Lai, T. Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, W. Hsu, J. Zhan
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引用次数: 6

Abstract

This paper presents a dual-band 2×2 WiFi transceiver in 28nm bulk CMOS. Achieved receiver and transmitter EVM floor at 5GHz for 160MHz per channel are −35dB and −33dB, respectively. The 2.4GHz integrated PA provides 26.5dBm saturated output power while its 5GHz counterpart delivers 26dBm. The 2.4GHz receiver features mixer first architecture while the transmitter includes a 2nd harmonic notch for emission control.
一个2×2 802.11ac WiFi收发器,支持每通道160MHz的28nm CMOS操作
本文提出了一种双频2×2 WiFi收发器。在每通道160MHz的5GHz条件下实现的接收机和发射机EVM下限分别为- 35dB和- 33dB。2.4GHz集成放大器提供26.5dBm饱和输出功率,而其5GHz对应器件提供26dBm饱和输出功率。2.4GHz接收器具有混频器第一架构,而发射器包括用于发射控制的第二谐波陷波。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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