Wen-Kai Li, Wei-Chia Chan, Tzung-Chuen Tsai, Hui-Hsien Liu, W. Chang, Chang-Ming Lai, T. Chiang, Chen-Lun Lin, Pi-An Wu, Hao-Wei Huang, Yen-Liang Yeh, Pang-Ning Chen, Jui-Lin Hsu, Sheng-Hao Chen, Chi-Yun Wang, Yu-Hsien Chang, Tsung-Hsun Yang, Ruey-Bo Sun, W. Hsu, J. Zhan
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A 2×2 802.11ac WiFi transceiver supporting per channel 160MHz operation in 28nm CMOS
This paper presents a dual-band 2×2 WiFi transceiver in 28nm bulk CMOS. Achieved receiver and transmitter EVM floor at 5GHz for 160MHz per channel are −35dB and −33dB, respectively. The 2.4GHz integrated PA provides 26.5dBm saturated output power while its 5GHz counterpart delivers 26dBm. The 2.4GHz receiver features mixer first architecture while the transmitter includes a 2nd harmonic notch for emission control.
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