A digitally-tuned triple-band transformer power combiner for CMOS power amplifiers

Abstract

This paper presents the design and implementation of a CMOS transformer combiner that can be reconfigured to have similar efficiencies at widely separated frequency bands. Conventional transformer combiners employ a fixed tuning capacitance in the secondary network to optimize the efficiency for single frequency standard. In this work, we present a modified transformer combiner where digitally-switchable capacitors introduced at low-swing nodes within the combiner network enable frequency reconfiguration using CMOS switches. A 65 nm CMOS triple-band (2.5/3/3.5 GHz) power amplifier (PA) chip employing the reconfigurable combiner is also presented.