A 20dBm outphasing class E PA with high efficiency at power back-off in 65nm CMOS technology

A. Ghahremani, A. Annema, B. Nauta
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引用次数: 4

Abstract

This paper presents an outphasing class E PA (OEPA) in a 65nm CMOS technology, using a pcb transmission-line based power combiner. The OEPA can provide +20dBm output power from VDD=1.25V at 1.4GHz with 61% drain efficiency (DE) and 58% power added efficiency (PAE). We introduced a technique to rotate and shift power and efficiency contours of the two branch PAs that enables more than 44dB output power dynamic range, reduces switch voltage stresses compared to conventional OEPAs and enables 41% DE and 24% PAE at 12.5dB back-off.
在65nm CMOS技术中,具有高效率的功率回退的20dBm反相级epa
本文介绍了一种采用基于pcb在线传输的功率合成器的65纳米CMOS技术的消相级epa (OEPA)。OEPA可以在1.4GHz频率下提供+20dBm的VDD=1.25V输出功率,漏极效率(DE)为61%,功率附加效率(PAE)为58%。我们介绍了一种技术,可以旋转和改变两个支路PAs的功率和效率轮廓,使输出功率动态范围超过44dB,与传统的oepa相比,降低了开关电压应力,并在12.5dB回退时实现了41%的DE和24%的PAE。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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