An ultra low-cost 32-element 28 GHz phased-array transceiver with 41 dBm EIRP and 1.0–1.6 Gbps 16-QAM link at 300 meters

Abstract

This paper presents a 32-element phased-array architecture suitable for fifth-generation (5G) communication links. A 28–32 GHz silicon core chip is designed with 4 transmit/receive elements each with 14 dB gain control, 6-bit phase control, 4.6 dB measured noise figure (NF) in the RX mode and 10 dBm output 1 dB compression point (OP1dB) in the TX mode. Eight of these chips are flipped on a low-cost printed circuit board (PCB) with integrated antennas and Wilkinson combiners. The 32-element array has a measured EIRP of 41 dBm at P1dB, can scan to ±20° and ±50° in E- and H-planes, and comsumes 4.2 W and 6.4 W in RX and TX modes, respectively. The array is used in a 300 meter wireless link and achieves a data rate of 1.0–1.6 Gbps at 16-QAM for all scan angles with <12% EVM. To our knowledge, this represents state-of-the art in 28 GHz phased-arrays in terms of chip performance and integration level.