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2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

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An 80–106 GHz CMOS amplifier with 0.5V supply voltage 一个80-106 GHz的CMOS放大器，0.5V供电电压
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969079
K. Katayama, S. Amakawa, K. Takano, T. Yoshida, M. Fujishima, K. Hisamitsu, H. Takatsuka
{"title":"An 80–106 GHz CMOS amplifier with 0.5V supply voltage","authors":"K. Katayama, S. Amakawa, K. Takano, T. Yoshida, M. Fujishima, K. Hisamitsu, H. Takatsuka","doi":"10.1109/RFIC.2017.7969079","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969079","url":null,"abstract":"A low-power CMOS W-band amplifier that feeds on a 0.5-V supply is presented. It achieves a peak gain of 24.1 dB and consumes 12mW. This was made possible by (a) the use of Mie Fujitsu Semiconductor 55-nm CMOS technology with deeply depleted channel (DDC) MOSFETs, which are meant specifically for ultralow-power designs with sub-1V supply voltage, (b) high-ƒmax transistor layout, which gives about 1 dB higher gain in the W-band than the ordinary layout, and (c) single-ended negative-capacitance feedback technique, which gives wideband gain boosting comparable to its differential counterpart (with cross-coupled feedback capacitors) with half the power consumption of the latter.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121367448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A sub-1V, 2.8dB NF, 475µW coupled LNA for internet of things employing dual-path noise and nonlinearity cancellation 一种超低电压、2.8dB NF、475µW耦合物联网LNA，采用双路噪声和非线性消除
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969061
Mustafijur Rahman, R. Harjani
{"title":"A sub-1V, 2.8dB NF, 475µW coupled LNA for internet of things employing dual-path noise and nonlinearity cancellation","authors":"Mustafijur Rahman, R. Harjani","doi":"10.1109/RFIC.2017.7969061","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969061","url":null,"abstract":"A 0.7V low power LNA combines a 1∶3 frontend balun with dual-path noise and non-linearity cancellation for improved noise performance at low power. In traditional techniques only the noise of the main path is cancelled while the noise of the auxiliary path is minimized by using high power. In the proposed design, the noise and non-linearity of both the main and the auxiliary paths are mutually cancelled allowing for low power operation. The 2.8dB NF, −10.7dBm IIP3 LNA in TSMC's 65nm GP process consumes 475µW of power resulting in an FOM of 28.8dB which is 8.2dB better than the state of the art.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122615168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Envelope time-domain characterizations to assess in-band linearity performances of pre-matched MASMOS® power amplifier 包络时域特性评估带内线性性能的预匹配MASMOS®功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969003
F. Simbelie, V. Gillet, S. Laurent, P. Medrel, Y. Creveuil, M. Regis, M. Prigent, R. Quéré
{"title":"Envelope time-domain characterizations to assess in-band linearity performances of pre-matched MASMOS® power amplifier","authors":"F. Simbelie, V. Gillet, S. Laurent, P. Medrel, Y. Creveuil, M. Regis, M. Prigent, R. Quéré","doi":"10.1109/RFIC.2017.7969003","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969003","url":null,"abstract":"This paper reports on an innovative in-band linearity performances characterization dedicated to nonlinear RF power amplifiers, here, pre-matched MASMOS® power amplifier. It consists of a generic multi-tones test signal that emulates the statistical properties of the applicative signal and allows signal and intermodulation output component separation for in-band C/I (signal to intermodulation power ratio) calculation. Two types of tests are successively discussed. The first one are standards VSA-based measurement performed with a 16-QAM and 256-QAM modulated signal. Secondly, a specific multi-tones signal is presented and compared with the reference VSA measurement. It is shown that the proposed generic stimulus can be used to evaluate, in specific conditions, the in-band interferences that degrade the Error Vector Magnitude (EVM) in the case of a nonlinear link.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130372815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A precision 140MHz relaxation oscillator in 40nm CMOS with 28ppm/°C frequency stability for automotive SoC applications 精密140MHz弛豫振荡器，40nm CMOS, 28ppm/°C频率稳定，适用于汽车SoC应用
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969016
Dmytro Cherniak, R. Nonis, F. Padovan
{"title":"A precision 140MHz relaxation oscillator in 40nm CMOS with 28ppm/°C frequency stability for automotive SoC applications","authors":"Dmytro Cherniak, R. Nonis, F. Padovan","doi":"10.1109/RFIC.2017.7969016","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969016","url":null,"abstract":"The need for high-frequency, low-power, wide temperature range, precision on-chip reference clock generation makes relaxation oscillator topology an attractive solution for various automotive applications. This paper presents for the first time a 140MHz relaxation oscillator with robust-against-process-variation temperature compensation scheme. The high-frequency relaxation oscillator achieves 28 ppm/°C frequency stability over the automotive temperature range from −40 to 175°C. The circuit is fabricated in 40nm CMOS technology, occupies 0.009 mm2 and consumes 294µW from 1.2V supply.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116948833","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
A fully-integrated 94-GHz 32-element phased-array receiver in SiGe BiCMOS SiGe BiCMOS中完全集成的94 ghz 32元相控阵接收器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969097
J. Plouchart, Wooram Lee, Caglar Ozdag, Yigit Aydogan, M. Yeck, A. Cabuk, A. Kepkep, Emre Apaydin, A. Valdes-Garcia
{"title":"A fully-integrated 94-GHz 32-element phased-array receiver in SiGe BiCMOS","authors":"J. Plouchart, Wooram Lee, Caglar Ozdag, Yigit Aydogan, M. Yeck, A. Cabuk, A. Kepkep, Emre Apaydin, A. Valdes-Garcia","doi":"10.1109/RFIC.2017.7969097","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969097","url":null,"abstract":"A 94GHz phased array receiver IC in 130nm BiCMOS technology is reported. The design integrates 32 front ends with gain and phase control configurable using look-up table memory, two separate 16∶1 power combiner trees, two 94GHz to ∼10GHz (IF) down conversion mixers, an IF to baseband (BB) quadrature down conversion mixer, and a 42GHz PLL followed by a frequency doubler implementing the LO source. The IC occupies an area of 6.7mm×5.6mm and can either support a 32-element phased array or a 16-element polarimetric phased array if connected to 16 dual-polarized antennas. In on-wafer measurements at 94GHz and 25C, the design achieves maximum RF to IF array conversion gain of 39dB, maximum RF to BB array conversion gain of 69dB, 20dB of RF front-end gain programmability, NF of 6 dB, and RMS phase error <1.5° for a 5° phase step. Total power consumption varies from 3W to 4.6W from minimum to maximum RF front-end gain settings.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132951176","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A mixer-first receiver with enhanced selectivity by capacitive positive feedback achieving +39dBm IIP3 and <3dB noise figure for SAW-less LTE Radio 一种混频器优先接收器，通过电容式正反馈增强选择性，实现+39dBm IIP3和<3dB噪声系数，适用于无saw LTE无线电
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969072
Yuanching Lien, E. Klumperink, B. Tenbroek, J. Strange, B. Nauta
{"title":"A mixer-first receiver with enhanced selectivity by capacitive positive feedback achieving +39dBm IIP3 and <3dB noise figure for SAW-less LTE Radio","authors":"Yuanching Lien, E. Klumperink, B. Tenbroek, J. Strange, B. Nauta","doi":"10.1109/RFIC.2017.7969072","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969072","url":null,"abstract":"A mixer-first receiver enhanced with capacitive positive feedback is proposed to obtain a steeper filter roll-off and enhanced linearity, while keeping low noise figure. It covers all sub-6GHz cellular bands and achieves a high IIP3 of +39dBm and blocker 1dB gain compression point of +12dBm for a blocker frequency-offset of 80MHz at fLO=2GHz. The NF ranges from 2.4dB at fLO=1GHz to 5.4dB at fLO=6GHz. The chip has been fabricated in Globalfoundries 45nm SOI technology on a high resistivity substrate.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123070197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 23
An analysis of phase noise requirements for ultra-low-power FSK radios 超低功率FSK无线电的相位噪声要求分析
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969011
Xing Chen, Hun-Seok Kim, D. Wentzloff
{"title":"An analysis of phase noise requirements for ultra-low-power FSK radios","authors":"Xing Chen, Hun-Seok Kim, D. Wentzloff","doi":"10.1109/RFIC.2017.7969011","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969011","url":null,"abstract":"This paper presents an analysis of the influence of phase noise (PN) on FSK radios and derives the total PN requirement for a low power FSK link based on Bit Error Rate (BER) performance. A simple noise model is built, including phase noise and white noise from the AWGN channel, to analyze its influence on the BER of an ULP FSK RX. It shows that to achieve a 10−4 BER, the minimum PN requirement can be more relaxed than current synthesizer designs. The trade-off between PN, data rate, and frequency deviation of FSK modulation is also studied, showing how bandwidth can be traded for relaxed PN while maintaining the same spectral efficiency (bits/Hz). This result implies we could migrate from LC-VCOs to ring oscillators with a simple PLL for wireless communication using FSK and significantly reduce the power of radios. A chip was fabricated to test the accuracy of the model at different PN levels, showing agreement among theoretical analysis, simulations, and measurements.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124061477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
A 40GHz PLL with −92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter 40GHz锁相环，带内相位噪声为- 92.5dBc/Hz, rms抖动为104fs
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969009
Ying Chen, L. Praamsma, N. Ivanisevic, D. Leenaerts
{"title":"A 40GHz PLL with −92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter","authors":"Ying Chen, L. Praamsma, N. Ivanisevic, D. Leenaerts","doi":"10.1109/RFIC.2017.7969009","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969009","url":null,"abstract":"This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-µm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <−92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <−73dBc across the whole locking range.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123593084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A 73GHz PA for 5G phased arrays in 14nm FinFET CMOS 14nm FinFET CMOS中用于5G相控阵的73GHz PA
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969103
Steven Callender, S. Pellerano, C. Hull
{"title":"A 73GHz PA for 5G phased arrays in 14nm FinFET CMOS","authors":"Steven Callender, S. Pellerano, C. Hull","doi":"10.1109/RFIC.2017.7969103","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969103","url":null,"abstract":"This paper presents the design of an E-band PA in Intel 14nm FinFET/trigate CMOS process. Device layout optimizations are used to maximize device performance at mm-wave frequencies and overcome the impact of scaling on RF performance. Neutralization and low-k transformer-based matching networks are employed to improve gain and bandwidth. The PA achieves a peak gain of 11.9dB/16.7 dB at 71GHz with a bandwidth of 8.5GHz/7.4 GHz in low-gain/high-gain mode. At 71GHz, the measured Psat, OP1dB and peak PAE are 7.3dBm, 1.6dBm, and 8.3%, respectively.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121922857","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
A harmonic-selective wireless Full-Band-Capture receiver with digital harmonic rejection calibration 一种具有数字谐波抑制校准的谐波选择无线全带捕获接收机
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969008
Hao Wu, D. Murphy, H. Darabi
{"title":"A harmonic-selective wireless Full-Band-Capture receiver with digital harmonic rejection calibration","authors":"Hao Wu, D. Murphy, H. Darabi","doi":"10.1109/RFIC.2017.7969008","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969008","url":null,"abstract":"A 30mW Full-Band-Capture receiver based on harmonic selection is presented. The prototype receiver employs a 32-phase non-overlapping LO, and is capable of simultaneously receiving multiple wireless signals arbitrarily located between 600MHz and 3GHz. The receiver achieves 2.4 to 5dB NF and tolerates more than −10dBm out-of-band blockers. A digital harmonic rejection calibration is also proposed to overcome phase and amplitude mismatches in the 32-phase LO and down-conversion paths.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123036653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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