A 73GHz PA for 5G phased arrays in 14nm FinFET CMOS

Abstract

This paper presents the design of an E-band PA in Intel 14nm FinFET/trigate CMOS process. Device layout optimizations are used to maximize device performance at mm-wave frequencies and overcome the impact of scaling on RF performance. Neutralization and low-k transformer-based matching networks are employed to improve gain and bandwidth. The PA achieves a peak gain of 11.9dB/16.7 dB at 71GHz with a bandwidth of 8.5GHz/7.4 GHz in low-gain/high-gain mode. At 71GHz, the measured Psat, OP1dB and peak PAE are 7.3dBm, 1.6dBm, and 8.3%, respectively.