发布求助
文献互助 智能选刊 最新文献

2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)最新文献

筛选
英文 中文
An FD/FDD transceiver with RX band thermal, quantization, and phase noise rejection and >64dB TX signal cancellation 具有RX波段热、量化和相位噪声抑制和>64dB TX信号对消功能的FD/FDD收发器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969090
Sameet Ramakrishnan, Lucas Calderin, A. Niknejad, B. Nikolić
{"title":"An FD/FDD transceiver with RX band thermal, quantization, and phase noise rejection and >64dB TX signal cancellation","authors":"Sameet Ramakrishnan, Lucas Calderin, A. Niknejad, B. Nikolić","doi":"10.1109/RFIC.2017.7969090","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969090","url":null,"abstract":"A transceiver system with active cancellation of the TX signal for full duplex (FD) or frequency division duplex systems (FDD) is presented. A replica cancellation digital-to-analog converter and highly linear receiver with +25dBm OOB IIP3 enable FDD operation without a duplexer at TX power up to +17dBm, FD operation without a circulator up to +5dBm, and FD operation with a circulator up to +13dBm. In addition to providing over 64dB of RF cancellation for a 20MHz modulated TX signal, the front-end demonstrates techniques to cancel noise sources in the RX band, including 3dB reduction of the thermal noise from the self-interference cancellation circuits, >25dB cancellation of quantization noise from the digital TX, and >20dB cancellation of TX LO phase noise in the RX band.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"138 7","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120851696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS 一种用于5G相控阵的29 ~ 57ghz AM-PM补偿ab类功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969031
M. Vigilante, P. Reynaert
{"title":"A 29-to-57GHz AM-PM compensated class-AB power amplifier for 5G phased arrays in 0.9V 28nm bulk CMOS","authors":"M. Vigilante, P. Reynaert","doi":"10.1109/RFIC.2017.7969031","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969031","url":null,"abstract":"This paper presents a 29-to-57GHz (65% BW) AM-PM compensated class-AB power amplifier tailored for 5G phased arrays. Designed in 0.9V 28nm CMOS without RF thick top metal, the PA achieves a Psat=15.1dBm±1.6dB and |AM-PM|<1° from 29-to-57GHz, with a peak PAE of 24.2%. Techniques are studied to realize the required load impedance and distortion cancellation over the wide band of operation, while allowing 2-way power combining to further increase the delivered POUT. The very low AM-PM distortion of the realized PA enables up to 10.1, 8.9, 5.9dBm average POUT while amplifying a 1.5, 3, 6Gb/s 64-QAM respectively at 34GHz with EVM/ACPR better than −25dBc/−30dBc, without any digital pre-distortion.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122759121","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS 用于28GHz移动通信的40nm CMOS高效率线性功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969010
Yang Zhang, P. Reynaert
{"title":"A high-efficiency linear power amplifier for 28GHz mobile communications in 40nm CMOS","authors":"Yang Zhang, P. Reynaert","doi":"10.1109/RFIC.2017.7969010","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969010","url":null,"abstract":"This paper presents a high-efficiency, linear power amplifier (PA) for 28GHz mobile communications in 40nm CMOS technology. The design and layout are optimized for high linearity while maintaining high gain and output power. A capacitance neutralized differential pair with source degeneration inductor for linearity enhancement is discussed. The inductive degeneration technique greatly increases the optimal load impedance, which enables a low loss parallel power combining. The complete PA achieves a measured saturated output power of 18.1dBm with 41.5% power-added efficiency (PAE). With 6 Gb/s QAM-64 signals, the proposed PA achieves an average output power of 8.4dBm and 8.8% PAE, with −25 dBc EVM. All measurements are performed with a fixed bias condition.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129995109","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
V-band flip-chip pHEMT balanced power amplifier with CPWGMS-CPWG topology and CPWG Lange couplers 采用CPWGMS-CPWG拓扑结构和CPWG Lange耦合器的v波段倒装pHEMT平衡功率放大器
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969006
Wei-Ling Chang, Jen-Yi Su, C. Meng, Chia-Hung Chang, G. Huang
{"title":"V-band flip-chip pHEMT balanced power amplifier with CPWGMS-CPWG topology and CPWG Lange couplers","authors":"Wei-Ling Chang, Jen-Yi Su, C. Meng, Chia-Hung Chang, G. Huang","doi":"10.1109/RFIC.2017.7969006","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969006","url":null,"abstract":"A V-band balanced two-stage power amplifier MMICs with Lange couplers is demonstrated using 0.15 µm GaAs pHEMT technology in this paper. A CPWG-MS-CPWG topology with via holes at the transistors as the transition between coplanar waveguide with backside ground (CPWG) and microstrip (MS) is employed for the two-stage amplifier. CPWG is applied to realize the flip-chip transition interface for both input and output ports of the amplifier and interstage MS matching has the advantage of small size. The structure parameters of the CPWG Lange coupler and matching network are designed and optimized for power combining. Finally, a 60-GHz balanced two-stage power amplifier using a CPWG-MS-CPWG structure delivers the small signal gain of 18 dB, OP1dB of 12 dBm and Psat of 15 dBm.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"39 10","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121191408","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Circuit building blocks for efficient in-antenna power combining at 240 GHz with non-50 Ohm amplifier matching impedance 电路构建模块，用于240 GHz的高效天线内功率组合与非50欧姆放大器匹配阻抗
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969082
C. V. Vangerow, B. Goettel, H. Ng, D. Kissinger, T. Zwick
{"title":"Circuit building blocks for efficient in-antenna power combining at 240 GHz with non-50 Ohm amplifier matching impedance","authors":"C. V. Vangerow, B. Goettel, H. Ng, D. Kissinger, T. Zwick","doi":"10.1109/RFIC.2017.7969082","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969082","url":null,"abstract":"In this work active and passive circuit components suitable for efficient in-antenna power combining are investigated with focus on the matching impedance between the individual components. In the proposed concept, the input power is split by 1∶4 couplers with 12.5Ω output impedance, which enables a very broadband input matching of the following single-ended amplifiers. To combine the output power of the parallelized amplifiers, an eight-feed integrated lens antenna (ILA) with 70Ω input impedance is used, which allows for compact matching to the optimum load impedance of the amplifiers. The individual circuit components are realized in IHP's SG13G2 technology and show excellent agreement with the simulation results. The four times parallelized amplifier shows a gain of roughly 5.5 dB at 240GHz excluding coupler losses.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125785364","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 25–30 GHz 8-antenna 2-stream hybrid beamforming receiver for MIMO communication 用于MIMO通信的25 - 30ghz 8天线2流混合波束成形接收机
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969030
Susnata Mondal, Rahul Singh, A. Hussein, J. Paramesh
{"title":"A 25–30 GHz 8-antenna 2-stream hybrid beamforming receiver for MIMO communication","authors":"Susnata Mondal, Rahul Singh, A. Hussein, J. Paramesh","doi":"10.1109/RFIC.2017.7969030","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969030","url":null,"abstract":"This paper presents a 65 nm CMOS 25–30 GHz hybrid beamforming receiver with eight antenna inputs and two baseband output streams. The receiver uses the Cartesian-Combining architecture, which is introduced for two baseband streams. Each antenna signal is complex-weighted independently and combined with weighted signals from other antennas prior to downconversion. Each RF-domain complex weight is realized using a pair of 5-bit digitally controlled VGA's. The receiver achieves 34 dB conversion gain, 7.3 dB minimum noise figure, and 5 GHz of RF bandwidth while consuming only 27.5 mW power per antenna element (340 mW for the entire receiver). Two-element Cartesian-combining achieves a peak-to-null ratio of 20 dB. Use of mostly active phase shifting and combining approach made the design ultra-compact with 3.86 mm2 core area for entire 8-element 2-stream receiver.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127047702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
A simplified CMOS FET model using surface potential equations for inter-modulation simulations of passive-mixer-like circuits 采用表面电位方程的简化CMOS场效应管模型用于无源混频器样电路的互调仿真
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969035
Mahmood Baraani Dastjerdi, H. Krishnaswamy
{"title":"A simplified CMOS FET model using surface potential equations for inter-modulation simulations of passive-mixer-like circuits","authors":"Mahmood Baraani Dastjerdi, H. Krishnaswamy","doi":"10.1109/RFIC.2017.7969035","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969035","url":null,"abstract":"In many CMOS analog/RF circuits, such as passive mixers or N-path filters, the transistor operates as a switch. Switching circuits often experience source-drain reversal, and most transistor models exhibit discontinuities in second and higher-order derivatives of the drain current around zero drain-source bias. This introduces fundamental challenges in performing third-order inter-modulation distortion simulations. In this work, a method is presented to replace the factory models with equivalent surface potential models for static current in conjunction with a simple circuit to take into account second-order parasitics, namely, gate current and terminal capacitors. The modeling approach may be utilized even if device measurements are not available, is shown to be simultaneously more computationally efficient and accurate than prior approaches, and is validated through measurements from a 0.15–2.5GHz mixer-first receiver in 65nm CMOS that exhibits +34.8dBm out-of-band IIP3.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131651909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Crystal-free narrow-band radios for low-cost IoT 用于低成本物联网的无晶体窄带无线电
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969059
B. Wheeler, F. Maksimovic, Nima Baniasadi, Sahar M. Mesri, O. Khan, D. Burnett, A. Niknejad, K. Pister
{"title":"Crystal-free narrow-band radios for low-cost IoT","authors":"B. Wheeler, F. Maksimovic, Nima Baniasadi, Sahar M. Mesri, O. Khan, D. Burnett, A. Niknejad, K. Pister","doi":"10.1109/RFIC.2017.7969059","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969059","url":null,"abstract":"A transceiver was designed and fabricated in 65 nm CMOS to verify the feasibility of using a free running, on-chip LC tank as the local oscillator in an IEEE 802.15.4 transceiver. The elimination of the off-chip frequency reference is possible while still using a standards based narrow-band architecture. A free running LC tank is shown to have frequency stability better than ± 40 ppm in the absence of temperature changes. Demodulator-based feedback is implemented to allow a receiver to track transmitter drift due to varying environmental factors and phase noise. The modulation accuracy of a free-running open loop Minimum Shift Key (MSK) transmitter is shown to be within the limits set by IEEE 802.15.4.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"258 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116210863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
An FTNC receiver with +32.5dBm effective OB-IIP3 using baseband IM3 cancellation 一个使用基带IM3抵消的+32.5dBm有效OB-IIP3的FTNC接收机
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969002
Yudong Zhang, Jianxun Zhu, P. Kinget
{"title":"An FTNC receiver with +32.5dBm effective OB-IIP3 using baseband IM3 cancellation","authors":"Yudong Zhang, Jianxun Zhu, P. Kinget","doi":"10.1109/RFIC.2017.7969002","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969002","url":null,"abstract":"An IM3 cancellation technique is proposed and implemented in a 65nm CMOS 0.5–2.5GHz FTNC (frequency translational noise-cancelling) receiver with a wideband auxiliary path which also offers wideband interferer awareness. It achieves 8.8MHz BB BW, 40dB conversion gain, 3.3dB NF, +5dBm OB-IIP3, and −6.5dBm OB-B1dB without IM3 cancellation while consuming 36mW at 1.2V. Using IM3 cancellation, the equivalent OB-IIP3 for two-tone interferers is up to +32.5dBm with an extra 34mW of power consumption. For two −15dBm modulated interferers 18.8dB cancellation is demonstrated over 10MHz.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125634649","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Multi-standard 5 Gbps to 28.2 Gbps adaptive, single voltage SerDes transceiver with analog FIR and 2-tap unrolled DFE in 28nm CMOS 多标准5gbps至28.2 Gbps自适应，单电压SerDes收发器，模拟FIR和28nm CMOS的2抽头展开DFE
2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2017-06-04 DOI: 10.1109/RFIC.2017.7969007
M. Mahani, R. Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, P. Graumann, H. Ransijn, T. Dusatko, S. Ho, Philip Snyder, J. Joy, S. Nalluri, T. Zortea
{"title":"Multi-standard 5 Gbps to 28.2 Gbps adaptive, single voltage SerDes transceiver with analog FIR and 2-tap unrolled DFE in 28nm CMOS","authors":"M. Mahani, R. Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, P. Graumann, H. Ransijn, T. Dusatko, S. Ho, Philip Snyder, J. Joy, S. Nalluri, T. Zortea","doi":"10.1109/RFIC.2017.7969007","DOIUrl":"https://doi.org/10.1109/RFIC.2017.7969007","url":null,"abstract":"A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V power supply with an analog power consumption of 242.3 mW at 28.2 Gbps. Total area of the transceiver including the Clock Synthesis Unit (CSU) is 0.88 mm2.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134064803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信