M. Mahani, R. Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, P. Graumann, H. Ransijn, T. Dusatko, S. Ho, Philip Snyder, J. Joy, S. Nalluri, T. Zortea
{"title":"多标准5gbps至28.2 Gbps自适应，单电压SerDes收发器，模拟FIR和28nm CMOS的2抽头展开DFE","authors":"M. Mahani, R. Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, P. Graumann, H. Ransijn, T. Dusatko, S. Ho, Philip Snyder, J. Joy, S. Nalluri, T. Zortea","doi":"10.1109/RFIC.2017.7969007","DOIUrl":null,"url":null,"abstract":"A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V power supply with an analog power consumption of 242.3 mW at 28.2 Gbps. Total area of the transceiver including the Clock Synthesis Unit (CSU) is 0.88 mm2.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Multi-standard 5 Gbps to 28.2 Gbps adaptive, single voltage SerDes transceiver with analog FIR and 2-tap unrolled DFE in 28nm CMOS\",\"authors\":\"M. Mahani, R. Zavari, Su-Tarn Lim, David Hong, Karl Scheffer, P. Graumann, H. Ransijn, T. Dusatko, S. Ho, Philip Snyder, J. Joy, S. Nalluri, T. Zortea\",\"doi\":\"10.1109/RFIC.2017.7969007\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V power supply with an analog power consumption of 242.3 mW at 28.2 Gbps. Total area of the transceiver including the Clock Synthesis Unit (CSU) is 0.88 mm2.\",\"PeriodicalId\":349922,\"journal\":{\"name\":\"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-06-04\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2017.7969007\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2017.7969007","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Multi-standard 5 Gbps to 28.2 Gbps adaptive, single voltage SerDes transceiver with analog FIR and 2-tap unrolled DFE in 28nm CMOS
A low-power multi-standard transceiver in CMOS 28 nm is presented. The transceiver can be configured to cover the range from 5 Gbps to 28.2 Gbps. Both transmitter and receiver use a supply of 0.92 V. Transmitter uses a 3-tap Finite Impulse Response (FIR) filter and receiver uses a 3-tap analog FIR and 2-tap unrolled Decision Feedback Equalizer (DFE). The entire transceiver uses single level 0.92 V power supply with an analog power consumption of 242.3 mW at 28.2 Gbps. Total area of the transceiver including the Clock Synthesis Unit (CSU) is 0.88 mm2.
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
