A simplified CMOS FET model using surface potential equations for inter-modulation simulations of passive-mixer-like circuits

In many CMOS analog/RF circuits, such as passive mixers or N-path filters, the transistor operates as a switch. Switching circuits often experience source-drain reversal, and most transistor models exhibit discontinuities in second and higher-order derivatives of the drain current around zero drain-source bias. This introduces fundamental challenges in performing third-order inter-modulation distortion simulations. In this work, a method is presented to replace the factory models with equivalent surface potential models for static current in conjunction with a simple circuit to take into account second-order parasitics, namely, gate current and terminal capacitors. The modeling approach may be utilized even if device measurements are not available, is shown to be simultaneously more computationally efficient and accurate than prior approaches, and is validated through measurements from a 0.15–2.5GHz mixer-first receiver in 65nm CMOS that exhibits +34.8dBm out-of-band IIP3.