Ying Chen, L. Praamsma, N. Ivanisevic, D. Leenaerts
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引用次数: 8
摘要
本文展示了一个完全集成的40GHz低相位噪声锁相环，采用0.25 μ m SiGe:C BiCMOS技术实现。使用所提出的双增益PFD，在整个锁定范围内测量了1.4dB至3.2dB的带内相位噪声改善。该锁相环的带内相位噪声< - 92.5dBc/Hz，集成RMS抖动为104fs，比传统的PFD提高了25%。在整个锁定范围内，参考杂散< - 73dBc。
A 40GHz PLL with −92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter
This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-µm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <−92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <−73dBc across the whole locking range.
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