Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, J. Son, Bumman Kim
{"title":"Linear CMOS power amplifier at Ka-band with ultra-wide video bandwidth","authors":"Daechul Jeong, Kyunghoon Moon, Seokwon Lee, Byungjoon Park, Jihoon Kim, J. Son, Bumman Kim","doi":"10.1109/RFIC.2017.7969057","DOIUrl":null,"url":null,"abstract":"A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental nonlinear mixing. The PA, composed of 3 cascaded common-source (CS) stages, achieves peak PAE of 21.8% at output power of 14 dBm with 22 dB gain. The 3rd order inter-modulation distortion (IMD3) at an output power of 5 dBm is under −30 dBc for a video bandwidth of 1 GHz. The PA and LDO are fabricated in a 65 nm CMOS process and occupy 0.53 mm2.","PeriodicalId":349922,"journal":{"name":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2017.7969057","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
A highly linear power amplifier (PA) with ultra-wide video bandwidth is designed at a Ka-band for 5G application. To get a high linearity with high efficiency, a deep class-AB topology with 2nd harmonic control circuits is employed, reducing the 3rd order nonlinearity. Further, an efficient low-drop out (LDO) regulator is proposed to suppress the memory effect generated by the envelope and fundamental nonlinear mixing. The PA, composed of 3 cascaded common-source (CS) stages, achieves peak PAE of 21.8% at output power of 14 dBm with 22 dB gain. The 3rd order inter-modulation distortion (IMD3) at an output power of 5 dBm is under −30 dBc for a video bandwidth of 1 GHz. The PA and LDO are fabricated in a 65 nm CMOS process and occupy 0.53 mm2.