A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah in 65nm CMOS

A fully integrated reconfigurable low-power Sub-GHz transceiver for 802.11ah is presented. The receiver uses the low-IF/zero-IF reconfigurable architecture to support 1, 2 and 8MHz signal bandwidth, and the needed number of the Op-Amps in the analog baseband is reduced to 3 while providing 4th-order channel filtering and programmable gain amplification. The transmitter uses the digital polar architecture, with the open-loop phase modulator to support wide signal bandwidth and the inverse Class-D digital power amplifier to enhance the power efficiency. A Class-C VCO with dynamic gate bias technique for robust start-up and AFC-assisted oscillation amplitude control technique is used in the fractional-N PLL frequency synthesizer. The transceiver has been implemented in 65nm CMOS. The measured results show that the receiver achieves <3.89dB NF and 47dB image rejection, and the frequency synthesizer achieves −127.8dBc/Hz phase noise at 1MHz offset and −94.6dBc/Hz in-band phase noise from a 1.536GHz carrier. The transmitter demonstrates 6.98% EVM for 900MHz pi/4-DQPSK signals at 6.3 dBm output power without pre-distortion. The receiver and the frequency synthesizer consume 6.4mA and 5.5mA current from a 1.2V power supply, respectively, and the DPA in the transmitter achieves 51.7% drain efficiency at 17.1dBm peak output power.