A wideband linear direct digital RF modulator using harmonic rejection and I/Q-interleaving RF DACs

M. Mehrpoo, M. Hashemi, Y. Shen, R. van Leuken, M. Alavi, L. D. de Vreede
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引用次数: 8

Abstract

This paper presents a wideband linear direct digital RF modulator (DDRM) in 40nm CMOS technology. It features an advanced 2nd-order-hold interpolation filter and I/Q-interleaving harmonic rejection RF DACs. The 2×9-bit DDRM core occupies 0.21mm2 and consumes only 110mW at 1 GHz. Within the 0.9–3.1GHz frequency range, the peak output power reaches +9.2dBm and the 3rd/5th harmonic rejection, C-IMD3, and OIP3 are respectively better than 30 dB, −44 dBc, and +25 dBm. The EVM and ACPR at 3 GHz for a 57-MHz 64-QAM signal are better than −30 dB and −45 dB, respectively, and ACPR remains as low as −44 dBc up to a wide bandwidth of 110 MHz.
采用谐波抑制和I/ q交错射频dac的宽带线性直接数字射频调制器
提出了一种基于40nm CMOS技术的宽带线性直接数字射频调制器(DDRM)。它具有先进的二阶保持插值滤波器和I/ q交织谐波抑制射频dac。2×9-bit DDRM核心占地0.21mm2,在1ghz时仅消耗110mW。在0.9 ~ 3.1 ghz频率范围内,峰值输出功率达到+9.2dBm, 3 /5次谐波抑制、C-IMD3和OIP3分别优于30 dB、−44 dBc和+25 dBm。对于57mhz的64-QAM信号,3ghz时的EVM和ACPR分别优于- 30 dB和- 45 dB,在110mhz的带宽下,ACPR保持在- 44 dBc。
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