A 3.4Mbps NFC card emulator supporting 40mm2 loop antenna

Abstract

For compact integration of 13.56MHz NFC functionality in mobile devices, a small planar loop antenna is a necessity. Active load modulation (ALM) is a commonly adopted technique to boost load modulation amplitude to overcome weak inductive coupling in small antennas. However, due to the challenges of phase synchronization, ALM is mainly limited to low data rate NFC applications. This paper describes the challenges of supporting NFC Very High Bit Rate (VHBR) Card Emulation Mode (PICC) in small antennas. An ultra-fast retimed phase synchronization PLL technique is proposed to overcome the technical challenges of ALM for high data rate uplink transmission. A sub-sampling ADC topology is implemented as VHBR ASK envelope demodulator. A clock extractor-based PLL provides precise synchronized continuous clock to the high speed sub-sampling ADC for accurate demodulation of all ASK envelopes with modulation index (MI) ranging from 8% to 100%.