Peaking PA bias circuit for an APT CMOS Doherty PA

Abstract

This paper presents a peaking PA bias circuit for an Average Power Tracking (APT) CMOS Doherty PA, where the common supply voltage changes as the target average power changes. In order to have Doherty efficiency characteristics with APT, the peaking PA must have an adaptive bias circuit that shifts the bias as the supply voltage changes, activating the peaking PA at the correct backoff (6dB) from the Posat for that supply voltage. This bias circuit is demonstrated on a CMOS Doherty PA using standard 0.18um SOI. With the proposed bias circuit, the Doherty PA has specification compliant WCDMA performance (with DPD) up to 29dBm Pout, with 40–50% PAE (from 25–29dBm Pout) as the supply voltages ranges from 1.5V to 4V.