A 12-b, 1-GS/s 6.1 mW current-steering DAC in 14 nm FinFET with 80 dB SFDR for 2G/3G/4G cellular application

Jaekwon Kim, W. Jang, Yanghun Lee, Seunghyun Oh, Jongwoo Lee, T. Cho
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引用次数: 6

Abstract

A 14nm FinFET CMOS 12-b current-steering digital-to-analog (DAC) for 2G/3G/4G cellular applications is presented. A bit segmentation of 6-bit thermometer and 6-bit binary is adopted, and it utilizes the dynamic element matching (DEM) technique to suppress the spurious tones caused by the current source mismatches in 3-D FinFETs. In addition, to keep the voltage drop across each transistor within long-term reliability limit, output switches are designed with shielding transistors while achieving make-before-break operation with the proposed low crossing point level shifter. The active area of a single DAC is 0.036 mm2, and its power consumption is 6.1 mW with SFDR of 80 dBc.
12-b, 1-GS/s 6.1 mW电流转向DAC, 14nm FinFET, 80db SFDR,适用于2G/3G/4G蜂窝应用
介绍了一种用于2G/3G/4G蜂窝应用的14nm FinFET CMOS 12b电流转向数模(DAC)。采用6位温度计和6位二进制的位分割方法,利用动态单元匹配(DEM)技术抑制三维finfet中电流源不匹配引起的杂散。此外,为了使每个晶体管的电压降保持在长期可靠性范围内,输出开关设计了屏蔽晶体管,同时使用所提出的低交叉点电平移位器实现了先闭合后断开的操作。单个DAC的有效面积为0.036 mm2,功耗为6.1 mW, SFDR为80 dBc。
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