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2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)最新文献

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Electron beam inspection: CDU dual-mode inspection and lithography ghost image detection 电子束检测:CDU双模检测及光刻伪像检测
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373162
R. Hafer, O. Patterson, Derek McKindles, Brian Yueh-Ling Hsieh
{"title":"Electron beam inspection: CDU dual-mode inspection and lithography ghost image detection","authors":"R. Hafer, O. Patterson, Derek McKindles, Brian Yueh-Ling Hsieh","doi":"10.1109/ASMC.2018.8373162","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373162","url":null,"abstract":"For a recent replacement metal gate (RMG) FINFET technology using an SOI substrate, two cases are reviewed using CD uniformity (CDU), a high throughput CD measurement technique using an e-beam inspection tool. In the first case, a CD is measured in the same process tooling as the defect inspection. The SRAM gate CD is shown to correlate strongly with defectivity, which affects the RMG formation. In this FINFET technology, the high aspect ratio of the gate makes removing the dummy gate very difficult. Residue is left behind, especially in multi-fin structures. The CD variation across wafer is shown, and inversely correlates with the observed defect density. In the second case, CDU is used to confirm and validate the fix for a latent-image ('ghost image') yield issue.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Process queue time control, reactive or proactive? 流程队列时间控制，是被动的还是主动的?
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373185
Chienfan Yu, Laura Bauman, V. Jophlin-Gut, G. Oakley, Michael Carbonnell, Z. Sowinski, E. Sherwood, Katherine Hawkins, Ryan Kelly, Rebekah Sheraw
{"title":"Process queue time control, reactive or proactive?","authors":"Chienfan Yu, Laura Bauman, V. Jophlin-Gut, G. Oakley, Michael Carbonnell, Z. Sowinski, E. Sherwood, Katherine Hawkins, Ryan Kelly, Rebekah Sheraw","doi":"10.1109/ASMC.2018.8373185","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373185","url":null,"abstract":"Process queue time control is a trade-off between defect and tool utilization. Three cases of queue time sensitivity discovered in active silicon (RX) module in our fab are discussed in this paper which led us to take a more pro-active approach to impose queue time control.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"216 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113991115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Wafer backside cleaning for defect reduction and litho hot spots mitigation: DI: Defect inspection and reduction 硅片背面清洁以减少缺陷和光刻热点;DI:缺陷检查和减少
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373151
Elango Balu, W. Tseng, David Jayez, J. Mody, K. Donegan
{"title":"Wafer backside cleaning for defect reduction and litho hot spots mitigation: DI: Defect inspection and reduction","authors":"Elango Balu, W. Tseng, David Jayez, J. Mody, K. Donegan","doi":"10.1109/ASMC.2018.8373151","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373151","url":null,"abstract":"With each new advanced technology node, minimum feature sizes continue to shrink. As a result, the devices become denser and exposure tool's depth of focus decreases — making lithography one of the most crucial modules in the process flow. Hence, the elimination of hot spots triggered by problematic pattern regions based on optical simulation, by cleaning wafer backside is a critical issue that needs to be addressed to prevent significant yield degradation.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129037604","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Standardising utility savings 标准化公用事业节约
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373136
M. Czerniak, Andreas A. Neuber
{"title":"Standardising utility savings","authors":"M. Czerniak, Andreas A. Neuber","doi":"10.1109/ASMC.2018.8373136","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373136","url":null,"abstract":"As the semiconductor industry makes devices and integrated circuits (ICs) that are increasingly complex, a consequence has been that the number of processing steps is increasing, from 400 at 90nm to > 1000 in state-of-the-art designs [1], shown in Figure 1. Furthermore, despite many process steps becoming more utility (and especially electrical power) — efficient, the increasing number of times a wafer visits process chambers has resulted in the energy use per cm2 wafer area increasing, reversing the trend of previous years. Figure 2 illustrates this phenomenon, which is also exacerbated by the use of double and quadrupole patterning, 3D device stacking and the use of EUV in HVM (which reduces the number of process steps but is utility-intensive).","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"282 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116081780","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Impact of scribe line (kerf) defectivity on wafer yield 刻线缺陷对晶圆成品率的影响
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373180
F. Khatkhatay, Ludmila Popova, Chih-chieh Huang, H. Lee, Y. Zang, K. C. Ahn, C. Tsao, Tae Hoon Lee, Thirukumaran Mahalingam, Haiting Wang, Amit Gupta, Julie Lee, Towshif Ali, J. M. Kaule
{"title":"Impact of scribe line (kerf) defectivity on wafer yield","authors":"F. Khatkhatay, Ludmila Popova, Chih-chieh Huang, H. Lee, Y. Zang, K. C. Ahn, C. Tsao, Tae Hoon Lee, Thirukumaran Mahalingam, Haiting Wang, Amit Gupta, Julie Lee, Towshif Ali, J. M. Kaule","doi":"10.1109/ASMC.2018.8373180","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373180","url":null,"abstract":"Scribe line (also known as kerf or frame) is an area in a silicon wafer which is used to separate individual die at the end of wafer processing. This area also contains features which assist in the manufacturing process but are not present in a final product. Examples of such features include lithography alignment and overlay marks, thickness measurement pads and electric test macros. The overall design of scribe line features can be drastically different from the die layout. In the chemical mechanical polishing (CMP) process, regions of low pattern density have higher polishing rates compared to those of high pattern density, leading to overpolishing or \"dishing\". The scribe line, with intermittent regions of low and high pattern density, is naturally more prone to dishing, an issue which is exacerbated by thickness variation at the wafer edge. In this work, we present examples of how interaction between process variation and scribe line design can result in yield loss for the prime die.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116120536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Particle reduction in back end of line plasma-etching process: CFM: Contamination free manufacturing 粒子减少后端线等离子蚀刻工艺:CFM:无污染制造
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373167
L. Zou, Alex Vaghese, V. Pai, J. Shearer, S. Skordas
{"title":"Particle reduction in back end of line plasma-etching process: CFM: Contamination free manufacturing","authors":"L. Zou, Alex Vaghese, V. Pai, J. Shearer, S. Skordas","doi":"10.1109/ASMC.2018.8373167","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373167","url":null,"abstract":"Particle contamination within a plasma-etching chamber causes tool down time in semiconductor manufacturing. The purpose of this work is to investigate the sources of contamination and find an effective solution for Back End of Line (BEOL) processes and improve tool up time. Despite typical maintenance, such as cycling chamber, wiping Electric Static Chuck (ESC) components and replacing chamber consumable parts, particle contamination issue persisted. Contamination analysis and ESC examination suggested etch byproduct redeposition during chuck discharge step as root cause. Modifying the discharge step was found to reduce the particle failure rate from 50% to 7%. This significant improvement confirms redeposition on ESC during discharge step and particle resuspension from ESC surface is the primary source for the particle contamination issue.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125383598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Advantages of using big data in semiconductor manufacturing 大数据应用于半导体制造的优势
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373166
Gabe Villareal, James Na, Joe Lee, T. Ho
{"title":"Advantages of using big data in semiconductor manufacturing","authors":"Gabe Villareal, James Na, Joe Lee, T. Ho","doi":"10.1109/ASMC.2018.8373166","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373166","url":null,"abstract":"In semiconductor manufacturing, advanced analytics are widely practiced for root-cause analysis and optimization of processes. Big Data promises to provide manufacturers a more powerful platform to get quicker and more insightful results over the traditional RDBMS systems, but most manufacturers have not made the move to this new technology. This paper examines three separate studies by tier-1 semiconductor manufacturers on their Big Data experience. Key advantages of this emerging technology will be highlighted to illustrate how Big Data can help to increase efficiency and improve performance.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125886091","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
CD-TEM: Characterizing impact of TEM sample preparation on CD metrology CD-TEM:表征TEM样品制备对CD计量的影响
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373170
Anne Kenslea, Chris Hakala, Zhenxin Zhong, Yinggang Lu, J. Fretwell, Jack Hager, Chris Kang, Haiyan Tan, Weihao Weng, L. Dumas, I. Brooks
{"title":"CD-TEM: Characterizing impact of TEM sample preparation on CD metrology","authors":"Anne Kenslea, Chris Hakala, Zhenxin Zhong, Yinggang Lu, J. Fretwell, Jack Hager, Chris Kang, Haiyan Tan, Weihao Weng, L. Dumas, I. Brooks","doi":"10.1109/ASMC.2018.8373170","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373170","url":null,"abstract":"Few existing in-line CD metrology techniques can match the sub-surface 3D analytical capability provided by transmission electron microscopy (TEM). Recent developments in sample preparation and analysis have resulted in a fully automated TEM workflow that enables widespread use of TEM for critical dimension metrology (\"CD-TEM\"). To better understand the precision of the TEM workflow, this study explores the impact of variations in sample preparation (thickness, damage layer, and cut placement) on CD metrology and precision.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126672632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
High density epitaxial unwanted growth and its effect on planarization in FINFET process 高密度外延生长及其对FINFET工艺平面化的影响
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373183
Pit Fee Jao, C. Tsao, Ludmila Popova, Jagadeesh Yarramsetty, Brad Chen, S. Shintri, M. Hariharaputhiran, V. Kolagunta
{"title":"High density epitaxial unwanted growth and its effect on planarization in FINFET process","authors":"Pit Fee Jao, C. Tsao, Ludmila Popova, Jagadeesh Yarramsetty, Brad Chen, S. Shintri, M. Hariharaputhiran, V. Kolagunta","doi":"10.1109/ASMC.2018.8373183","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373183","url":null,"abstract":"While epitaxial growth enhances carrier mobility of PMOS devices, it introduces an unwanted growth (UG) defect which is an artifact of Silicon Germanium (SiGe) component that becomes a yield detractor in high volume manufacturing. This paper describes the effect of high density UG defect on downstream CMP processes, detection methods using both defect scan and in-situ metrology. Use of high resolution defect scans and high throughput inline metrology was the key to detection of non-conforming material.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123705844","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep learning based automatic defect classification in through-silicon Via process: FA: Factory automation 基于深度学习的硅通孔工艺缺陷自动分类:FA:工厂自动化
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373144
Joongsoo Kim, Sihwan Kim, Namyeong Kwon, Hyohyeong Kang, Yongduk Kim, C. Lee
{"title":"Deep learning based automatic defect classification in through-silicon Via process: FA: Factory automation","authors":"Joongsoo Kim, Sihwan Kim, Namyeong Kwon, Hyohyeong Kang, Yongduk Kim, C. Lee","doi":"10.1109/ASMC.2018.8373144","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373144","url":null,"abstract":"Deep Neural Network technology has shown impressive performance in visual recognition problems such as defect image classification that depends on the skills and experiences of individual inspectors. We selected a Through-Silicon Via (TSV) process which has relatively few defect types to adapt deep networks as the first test bed. In this paper, we propose Convolutional Neural Network (CNN)-based defect image classification model derived from Residual Network which ranked first in image classification competitions such as ILSVRC and COCO 2015 with 4.62% test error. However, merely bringing the well-known architecture to the defect classification task was unable to resolve dataset problems: imbalance, ambiguity and inconsistency. We maximized the classification performance to 97.1% accuracy on the long-term dataset by optimizing classifier and cleansing the dataset. Our model can lessen defect classification work done by human by as much as 78.6%.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122182950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
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