2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)最新文献

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Detection of thermal donors from electrically active oxygen interstitials by optical second harmonic generation 利用光学二次谐波产生法检测电活性氧间隙的热给体
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373208
M. Lei, Jacqueline Zou, Justin Lee, J. Changala, B. Larzelere
{"title":"Detection of thermal donors from electrically active oxygen interstitials by optical second harmonic generation","authors":"M. Lei, Jacqueline Zou, Justin Lee, J. Changala, B. Larzelere","doi":"10.1109/ASMC.2018.8373208","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373208","url":null,"abstract":"Substrate resistivity stability has become the most critical control for radio frequency (RF) device manufacturing. In this paper, we demonstrate nonlinear optics based metrology to measure electrically active oxygen interstitial sites (Oi) in high resistive bulk Si wafers, which are vulnerable to electric and mechanical property drift during device fabrication. Time dependent second harmonic generation (TD-SHG) governed by electric-field induced second harmonic (EFISH) effect provides consistent detection of thermal donors originating from Oi distributed near Si interface. The successful concept proof can be extended to test pad design for in-line monitor of substrate resistivity variations from annealing processes.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123929732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A first-time exploration into sequenced multimodality saves big data for high-quality wafer-manufacturing 首次探索顺序多模态为高质量的晶圆制造节省了大数据
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373211
L. Sheng, Wei Pan
{"title":"A first-time exploration into sequenced multimodality saves big data for high-quality wafer-manufacturing","authors":"L. Sheng, Wei Pan","doi":"10.1109/ASMC.2018.8373211","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373211","url":null,"abstract":"The sequenced multimodality has been for the first time proposed and explored for effectively identifying the problematic tools in wafer processing. To demonstrate the merits and values of practicing this new concept, two case studies in product yield and in inline reliability were provided in detail. This new methodology can help save big data for enhancing the quality of wafer manufacturing.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"478 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129098015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Measuring the wafer temperature in HVM process tools using a new approach with automated wireless HighTemp-400 and EtchTemp-SE wafer systems 采用自动化无线HighTemp-400和EtchTemp-SE晶圆系统的新方法测量HVM工艺工具中的晶圆温度
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373138
D. Y. Kim, J. Kim, D. Chu, Dong Hong
{"title":"Measuring the wafer temperature in HVM process tools using a new approach with automated wireless HighTemp-400 and EtchTemp-SE wafer systems","authors":"D. Y. Kim, J. Kim, D. Chu, Dong Hong","doi":"10.1109/ASMC.2018.8373138","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373138","url":null,"abstract":"As the technology nodes become smaller it is becoming more important to control all aspects of influencing parameters for the deposition of thin films using CVD tools and for plasma etch tools. This is especially important in a high volume manufacturing (HVM) environment with new tool installations and the need to achieve production ramp timelines. Controlling tool parameters including chamber wafer temperature is critical for fast ramp to production. Production ramp up cycle time is very important. Chamber matching in process tools is becoming a critical path item for production ramp. Monitoring chamber temperature is one of the process control parameters for thin films, plasma etch, diffusion, and clean process tools. The current method of measuring wafer temperature is manual and time consuming. Table 1 shows the Manual versus Automation method comparison. KLA-Tencor's new Factory Automation System (Fig. 1) helps simplify and automate chamber temperature data collection, supporting chamber matching activities for high volume fab ramps. This automation system utilizes a host manufacturing execution system (MES) to send Process Job/Control Job commands to SensArray FOUPs and delivers wafers via overhead hoist transfer (OHT) to process tools to collect temperature data. Upon return of the Automation FOUP and wafer, temperature data are automatically uploaded to the MES system.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129829803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization Ti/TiN凹凸缺陷形成机理及蚀刻工艺优化消除研究
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373147
Lili Wu, Yuan-Chieh Chiu, Zusing Yang, Sheng-Yuan Chang, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu
{"title":"Study of Ti/TiN bump defect formation mechanism and elimination by etch process optimization","authors":"Lili Wu, Yuan-Chieh Chiu, Zusing Yang, Sheng-Yuan Chang, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu","doi":"10.1109/ASMC.2018.8373147","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373147","url":null,"abstract":"Subtle Ti/TiN bump defects are observed after thermal annealing in the development step of a back-end-of-line (BEOL) via metallization. It disturbs the endpoint detection of a sequential tungsten (W) chemical-mechanical planarization (CMP) process and results in W residue on the surface of the wafer. SIMS analysis conducted before Ti/TiN deposition indicates the presence of high concentrations of fluorine (F) atoms that have already doped into the oxide film after the via hole plasma etching process, even in the presence of an amorphous carbon hard-mask. The doped F species could diffuse out of the surface region, and then react with as-deposited Ti/TiN to form volatile TiF4 during high-temperature annealing. As a result, severe metallic bump-like defects are observed. In this study, we report that the formation of the metallic bump defect is correlated to both the RF bias frequency, and the RF bias power applied in the capacitive-coupled fluorocarbon plasma via feature etching.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121765811","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Advanced Materials1 先进Materials1
2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 1900-01-01 DOI: 10.1109/asmc.2018.8373184
D. Rhodes, S. Chowdury, S. Yea, J. Guerrero, Peter Smith, N. Bushnell
{"title":"Advanced Materials1","authors":"D. Rhodes, S. Chowdury, S. Yea, J. Guerrero, Peter Smith, N. Bushnell","doi":"10.1109/asmc.2018.8373184","DOIUrl":"https://doi.org/10.1109/asmc.2018.8373184","url":null,"abstract":"Electroless nickel immersion gold (ENIG) has emerged as a leading surface finish for under bump metallization (UBM). An ENIG surface typically exhibits excellent planarity, good electrical characteristics, wettability for solder, and Al-wire bondability. Reliability and performance of ENIG systems have been extensively reported at temperatures below 250°C, however information is not readily available about its reliability at higher temperatures. In this paper, thermal behavior of electroless Ni/Au and electroless Ni/Pd/Au during solder reflow processing at temperatures of up to 350°C was characterized. Wafer level evaluations were completed using optical microscopy and FIB cross-sectional SEMs, while packaged devices were subjected to standard reliability tests. Electroless Ni began to exhibit signs of cracking when exposed to temperatures of 350°C under certain conditions. Based on these findings, we propose ENIG material structures and maximum processing temperatures to eliminate cracking. Power devices manufactured with ENIG metallization can be capable of passing JEDEC qualification when implemented with these design parameters.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130203627","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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