F. Khatkhatay, Chih-chieh Huang, Ludmila Popova, Jongyoon Yoon, Thomas Zalocha, Phillip Tatti, Krishan Gopal, Hongliang Shen, Ho Young Song, Amit Gupta
{"title":"Leveraging focus spot monitoring Data in FEOL to resolve a high impact MOL defect: DI: Defect inspection and reduction","authors":"F. Khatkhatay, Chih-chieh Huang, Ludmila Popova, Jongyoon Yoon, Thomas Zalocha, Phillip Tatti, Krishan Gopal, Hongliang Shen, Ho Young Song, Amit Gupta","doi":"10.1109/ASMC.2018.8373181","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373181","url":null,"abstract":"As feature sizes shrink in 14nm technology and beyond, focus window limited immersion lithography steps like those in the middle of line (MOL) are most susceptible to hotspots caused by small localized variations in wafer topography. Hotspots in MOL are almost always killer, with a near 100% probability of the entire die failing due to the presence of a single hotspot defect. Focus spots are identified by the leveling system in the lithography scanner and the reported as a fault detection and classification (FDC) signal, driving wafer disposition and tool actions. Comprehensive reporting of focus spot signals opens up the possibility of utilizing high volume focus spot data in lieu of defect data where spatially unique hotpsot signals may be lost in the random baseline defectivity. We have analyzed focus spot data collected at a lower impact front end of line (FEOL) step to drive down hotspots at a high impact MOL step, both of which are affected by incoming defectivity due to repeat passes on a common identified tool. This work is an example of the smart resolution of a cross-module contamination issue by innovatively leveraging high volume focus spot monitoring data.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126916723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Lam, Michael Zhao, Ski Sim, K. K. Gan, T. Ho, Joe Lee
{"title":"The value and effectiveness of sensor trace analytics in solving yield impact issues: A case study","authors":"H. Lam, Michael Zhao, Ski Sim, K. K. Gan, T. Ho, Joe Lee","doi":"10.1109/ASMC.2018.8373212","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373212","url":null,"abstract":"Improving and maintaining production yield is critical for any manufacturing, therefore, one of the key responsibilities for engineers working in a semiconductor fab is to solve wafer yield issues in a timely manner. Traditional approach in root cause analysis requires multiple tools, multiple steps, and multiple domain resources. Time to solve a wafer yield issue could require days or weeks. To address this, engineers have started leveraging advanced data analytic software solutions to gain better insights and to help expedite the root cause analysis process. In this paper, the advantages of using a trace analytics software tool for root cause analysis is illustrated through an actual use case.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129542531","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Xiaoxiao Zhang, Mert Karakoy, K. Wu, Zhuangfei Chen, Zhenhua Ge, Navi Krishnan, Amit Siany, S. Levi, I. Schwarzband, R. Kris
{"title":"Inline detection for FinFET gate poly footing using e-Tilt metrology","authors":"Xiaoxiao Zhang, Mert Karakoy, K. Wu, Zhuangfei Chen, Zhenhua Ge, Navi Krishnan, Amit Siany, S. Levi, I. Schwarzband, R. Kris","doi":"10.1109/ASMC.2018.8373196","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373196","url":null,"abstract":"Advanced FinFET device architecture generates new profile control requirement in 1× node and beyond. The corner at the intersection between the Gate and Fin is critical geometry for device yield and reliability. The residue-free corner at Gate-Fin interface after Polysilicon gate etch is desirable yet also a known challenge to detect and control. Current detection methods for gate poly footing, also known as gate skirt, are destructive with long turnaround time, resulting in slow progress in process development and high-volume process control. To meet the gap, e-Tilt imaging technique along with corner rounding algorithm has been developed on CDSEM platform to visualize and quantify residue at fin-gate intersection (poly-footing). In this paper, we'll discuss the challenges, approaches, and results associated with the first-in-industry implementation of the inline poly-footing detection within a HVM Fab. Two sets of DOEs (Design of Experiment) were conducted to validate the sensitivity to Etch recipes and Etch Chambers. The accuracy and precision of the poly-footing measurement were qualified with correlation to commonly used hammer test results and eTest results. Future study includes precision and throughput improvement to meet the need of 1× node.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122346250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Bernd Waschneck, André Reichstaller, Lenz Belzner, Thomas Altenmüller, T. Bauernhansl, Alexander Knapp, A. Kyek
{"title":"Deep reinforcement learning for semiconductor production scheduling","authors":"Bernd Waschneck, André Reichstaller, Lenz Belzner, Thomas Altenmüller, T. Bauernhansl, Alexander Knapp, A. Kyek","doi":"10.1109/ASMC.2018.8373191","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373191","url":null,"abstract":"Despite producing tremendous success stories by identifying cat videos [1] or solving computer as well as board games [2], [3], the adoption of deep learning in the semiconductor industry is moderatre. In this paper, we apply Google DeepMind's Deep Q Network (DQN) agent algorithm for Reinforcement Learning (RL) to semiconductor production scheduling. In an RL environment several cooperative DQN agents, which utilize deep neural networks, are trained with flexible user-defined objectives. We show benchmarks comparing standard dispatching heuristics with the DQN agents in an abstract frontend-of-line semiconductor production facility. Results are promising and show that DQN agents optimize production autonomously for different targets.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115036400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Forging basic elements of cyber-physical systems in industry 4.0 with parametric characterization for FDC","authors":"K. Hui, Leo Ke, S. Sheen","doi":"10.1109/ASMC.2018.8373145","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373145","url":null,"abstract":"Industry 4.0 builds its entirety on the foundation stones of cyber-physical systems and the key to their realizations depend critically on the capability of constructing functioning models of the physical systems. We present an alternative approach to the efficient construction of sufficiently accurate engineering models to capture the governing process dynamics from the available data-streams of semiconductor manufacturing tools. Characterizations of these dynamic parameters provide different insights from those static features of conventional applications of elementary statistics, including their inferences. It also enables integrated formulation of concurrent process-equipment controls, in addition to the wider scope and deeper insights of effective FDC applications.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125771073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Nanoprober image based localization techniques for SOI technology","authors":"S. Pendyala, S. Lucarini, M. Tenney","doi":"10.1109/ASMC.2018.8373218","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373218","url":null,"abstract":"As we continue scaling down in technology, non-visible defects are dominating our defect paretos and nanoprobing has become an essential part of Failure Analysis [1]. However, nanoprobing can become highly time consuming if the defect is not localized to a few devices. Traditional localization techniques like SEM based Voltage Contrast and AFM based Current Imaging have been employed to localize defects on Bulk Semiconductor Technology. These techniques cannot be used as is for localizing defects on SOI technology as there is no direct path to ground from the SOI to the sample chuck. This paper will discuss two different Atomic Force Probe (AFP) based localization techniques that have been successfully implemented to localize defects on SOI Technology. The first technique is Capacitance based top-down Scanning Capacitance Localization also known and Nanoprobe Capacitance Voltage Spectroscopy (NCVS). The second technique is a Current Imaging based Pico-Current Localization Technique (also known as Conductive AFM) that has been modified to localize defects on SOI","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127730071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A systematic approach to secure data collection across an OEM's fleet of tools","authors":"Doug Suerich, Veronica Consens","doi":"10.1109/ASMC.2018.8373164","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373164","url":null,"abstract":"This paper discusses the approaches that a team at PEER Group took to design and implement a secure data management system intended to collect data from tools installed at various fabs in different geographic locations and to move that data to a cloud-based storage system. The motivation for the work was to find the best way to match equipment performance across a global fleet of tools using modern analytics on the data to enable predictive decision-making. Gathering data and feeding it into remote analytics software to perform fleet-wide comparisons presents familiar obstacles related to IP protection, the management of big data, and implementation risk. The majority of the effort in creating such a data collection system did not lie in the collection or movement of the data, but rather in the systematic identification and assessment of objections to data sharing in a notoriously secretive industry. By explicitly addressing each of the concerns related to secure data sharing, we were able to create a system that allowed for limited collection of data in a means acceptable to all stakeholders.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130430750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Ramadout, D. Wehella-gamage, T. Staiger, K. Babich, H. Moll, J. Wallner, O. Patterson
{"title":"A multi-factorial approach for middle-of-line design rule validation and optimization in 22FDX®","authors":"B. Ramadout, D. Wehella-gamage, T. Staiger, K. Babich, H. Moll, J. Wallner, O. Patterson","doi":"10.1109/ASMC.2018.8373216","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373216","url":null,"abstract":"In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX®, novel Middle-of-Line (MOL) constructs have been specifically enabled. SingleDiffusion Break and Gate Tie-Down constructs and their specific design-to-process validation requirements are described. In particular, contact punch-through is investigated and validated using electrical and E-beam inspection methods. As a second step, the Gate Tie-down is optimized thanks to layout Design of Experiments to provide optimal performance and density once implemented in Standard Cells.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132838755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Effective Epi process window monitoring by high resolution massive CDU metrology: Topic: AM (Advanced metrology)","authors":"Z. Y. Chen, T. Y. Chen, I. Holcman, Bruce Tseng","doi":"10.1109/ASMC.2018.8373152","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373152","url":null,"abstract":"Advanced technology with shrinking design rules and increasing multi-patterning steps introduce challenging process tolerances. Process marginality is in the form of Edge Placement Errors (EPE), Line Edge Roughness (LER), Line Width Roughness (LWR), Overlay and process induced pattern defects. Advanced metrology and monitoring techniques are needed to trace process induced critical pattern distortion within die, field and wafer. Massive sampling of critical pattern features (i.e. hot spots) measurements can be the solution for tight process margins monitoring. Many measurements across die, field and wafer can reveal clear signature of the process tools from film deposition, lithography, etch, chemical mechanical polishing and epitaxial growth indicate immerging process window marginality issues. Clear signature can be built from thousands to millions measurements. High resolution and throughput metrology tool is needed to provide capabilities in critical dimension uniformity (CDU) and overlay shift for Edge Placement Errors. Channel strain in continuous fin pitch reduction introduces new challenges in crystalline epitaxy growth. It is one of the most challenging tasks in process monitoring and control for lateral growth dimension, abnormal growth and shapes. Epi growth monitoring includes many measurement types and defect detection. A study of new monitoring method based on massive hotspot and CDU measurements is introduced. Examples of its implementation in Epitaxial growth module are provided for engineers to make effective actions in time.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123110526","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Dewei Xu, R. Srivastava, Ushasree Katakamsetty, E. G. de la Garza, H. Kim, R. Augur, R. Fox
{"title":"Optimization of BEOL R&C monitoring macros for accurate representation of circuit performance","authors":"Dewei Xu, R. Srivastava, Ushasree Katakamsetty, E. G. de la Garza, H. Kim, R. Augur, R. Fox","doi":"10.1109/ASMC.2018.8373150","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373150","url":null,"abstract":"R (line resistance) and C (coupling capacitance) parameters are among the critical parameter list or even wafer acceptance criteria in volume production. Process engineers rely on R and C monitoring macros to tune processes to meet targets and control specs. However, the performance and capability of the R and C macros are much impacted by their own design. Therefore, properly designed R and C monitoring macros to represent genuine R and C performance in the product are critical. In this study, we show R and C monitoring macros were designed to make sure the same metal density is implemented at the underlying metal layer (CA/CB level) and on-layer. Furthermore, the desired pattern density is desired to be set as representative of the prime die at areas of interest (for example, SRAM, logic/analog devices or other active circuits). Therefore, resulting metal line profiles are consistent and corresponding RC plots represent the genuine RC performance.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132658986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}