B. Ramadout, D. Wehella-gamage, T. Staiger, K. Babich, H. Moll, J. Wallner, O. Patterson
{"title":"A multi-factorial approach for middle-of-line design rule validation and optimization in 22FDX®","authors":"B. Ramadout, D. Wehella-gamage, T. Staiger, K. Babich, H. Moll, J. Wallner, O. Patterson","doi":"10.1109/ASMC.2018.8373216","DOIUrl":null,"url":null,"abstract":"In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX®, novel Middle-of-Line (MOL) constructs have been specifically enabled. SingleDiffusion Break and Gate Tie-Down constructs and their specific design-to-process validation requirements are described. In particular, contact punch-through is investigated and validated using electrical and E-beam inspection methods. As a second step, the Gate Tie-down is optimized thanks to layout Design of Experiments to provide optimal performance and density once implemented in Standard Cells.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2018.8373216","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
In order to allow competitive and low-cost designs in the 22nm FD-SOI technology 22FDX®, novel Middle-of-Line (MOL) constructs have been specifically enabled. SingleDiffusion Break and Gate Tie-Down constructs and their specific design-to-process validation requirements are described. In particular, contact punch-through is investigated and validated using electrical and E-beam inspection methods. As a second step, the Gate Tie-down is optimized thanks to layout Design of Experiments to provide optimal performance and density once implemented in Standard Cells.