Dewei Xu, R. Srivastava, Ushasree Katakamsetty, E. G. de la Garza, H. Kim, R. Augur, R. Fox
{"title":"Optimization of BEOL R&C monitoring macros for accurate representation of circuit performance","authors":"Dewei Xu, R. Srivastava, Ushasree Katakamsetty, E. G. de la Garza, H. Kim, R. Augur, R. Fox","doi":"10.1109/ASMC.2018.8373150","DOIUrl":null,"url":null,"abstract":"R (line resistance) and C (coupling capacitance) parameters are among the critical parameter list or even wafer acceptance criteria in volume production. Process engineers rely on R and C monitoring macros to tune processes to meet targets and control specs. However, the performance and capability of the R and C macros are much impacted by their own design. Therefore, properly designed R and C monitoring macros to represent genuine R and C performance in the product are critical. In this study, we show R and C monitoring macros were designed to make sure the same metal density is implemented at the underlying metal layer (CA/CB level) and on-layer. Furthermore, the desired pattern density is desired to be set as representative of the prime die at areas of interest (for example, SRAM, logic/analog devices or other active circuits). Therefore, resulting metal line profiles are consistent and corresponding RC plots represent the genuine RC performance.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"86 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2018.8373150","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
R (line resistance) and C (coupling capacitance) parameters are among the critical parameter list or even wafer acceptance criteria in volume production. Process engineers rely on R and C monitoring macros to tune processes to meet targets and control specs. However, the performance and capability of the R and C macros are much impacted by their own design. Therefore, properly designed R and C monitoring macros to represent genuine R and C performance in the product are critical. In this study, we show R and C monitoring macros were designed to make sure the same metal density is implemented at the underlying metal layer (CA/CB level) and on-layer. Furthermore, the desired pattern density is desired to be set as representative of the prime die at areas of interest (for example, SRAM, logic/analog devices or other active circuits). Therefore, resulting metal line profiles are consistent and corresponding RC plots represent the genuine RC performance.