Inline detection for FinFET gate poly footing using e-Tilt metrology

Abstract

Advanced FinFET device architecture generates new profile control requirement in 1× node and beyond. The corner at the intersection between the Gate and Fin is critical geometry for device yield and reliability. The residue-free corner at Gate-Fin interface after Polysilicon gate etch is desirable yet also a known challenge to detect and control. Current detection methods for gate poly footing, also known as gate skirt, are destructive with long turnaround time, resulting in slow progress in process development and high-volume process control. To meet the gap, e-Tilt imaging technique along with corner rounding algorithm has been developed on CDSEM platform to visualize and quantify residue at fin-gate intersection (poly-footing). In this paper, we'll discuss the challenges, approaches, and results associated with the first-in-industry implementation of the inline poly-footing detection within a HVM Fab. Two sets of DOEs (Design of Experiment) were conducted to validate the sensitivity to Etch recipes and Etch Chambers. The accuracy and precision of the poly-footing measurement were qualified with correlation to commonly used hammer test results and eTest results. Future study includes precision and throughput improvement to meet the need of 1× node.