Vijay Chowdhury, David Simionas, Kiera Fu, Janie Huang, P. Sun
{"title":"Trace metal contamination analysis of wafer edge and bevel by automated VPD ICP-MS: CFM: Contamination free manufacturing","authors":"Vijay Chowdhury, David Simionas, Kiera Fu, Janie Huang, P. Sun","doi":"10.1109/ASMC.2018.8373201","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373201","url":null,"abstract":"Wafer edge exclusion zone does not constitute any active usable die; nevertheless, it is a source of contamination as it comes into contact with processing equipment. Transition to copper interconnects and low-k dielectrics as well as decreasing gate lengths in Semiconductor manufacturing have resulted in bigger yield hits due to microcontamination from edge exclusion zone. The difficulty of evaluating contamination from edge and bevel of a wafer is well known even as the importance of contamination from these areas has increased. In this study, we will highlight the tools and the methods that we have employed in addressing this problem. We will also share the method detection limits and spike recoveries of trace metals achieved from silicon wafer bevel and edge through Inductively Coupled Plasma Mass Spectrometry (ICP-MS).","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"520 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116180187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
M. Liebens, J. Slabbekoorn, A. Miller, E. Beyne, M. Störring, S. Hiebert, A. Cross
{"title":"Defect learning methodology applied to microbump process at 20μm pitch and below","authors":"M. Liebens, J. Slabbekoorn, A. Miller, E. Beyne, M. Störring, S. Hiebert, A. Cross","doi":"10.1109/ASMC.2018.8373210","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373210","url":null,"abstract":"Over the last years, 3D TSV technology and 3D stacking have moved into the preproduction and yield ramp phase. The characterization of many of the different critical modules within the 3D stacking integration flows is becoming more and more crucial. Microbump dimensions are being scaled down to the pitch of 20µm and below. This scaling is required in order to achieve higher interconnect densities. For yielding vertical interconnects in die-to-die and die-to-wafer stacking, highly accurate and repeatable measurements and inspections of microbumps are an absolute must for this technology to become a viable industrial option. Microbump process control is usually a hybrid approach of inspecting the full wafer including all microbumps and specific microbump metrology. This eventually enables correct die classification and selection of known good die for further integration in 3D packages. Prior to being able to classify and disposition die based on microbump integrity, yield critical defect types need to be identified, defect mechanisms need to be understood and dimensional features impacting further processing need to be characterized. This paper addresses these requirements and elaborates on the applied defect learning methodology based on a significant amount of microbump process monitor wafers. Yield loss by every defect type was quantified and root causes for these yield critical defect types were discovered. From this analysis, further process improvement projects can be initiated, parameters for statistical process control derived and known good die for yielding die-to-die and die-to-wafer stacking can be identified and separated from failing die.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129859922","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Ackermann, B. Binder, J.J.E. Schmidt, Joerg Radecker, C. Caballero
{"title":"Hybrid clean for applied materials 200mm centura reduced pressure EPI application","authors":"T. Ackermann, B. Binder, J.J.E. Schmidt, Joerg Radecker, C. Caballero","doi":"10.1109/ASMC.2018.8373139","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373139","url":null,"abstract":"A new approach for post deposition in situ HCL cleaning the Applied Materials 200mm Reduced Pressure Epitaxy chamber was tested on a tool in a production environment within a joint CIP between Infineon Technology, Dresden and Applied Materials. This Hybrid Clean method utilizes three recent introduced hardware upgrades for the RP Epi Centura chamber. The items had been upgraded to enable Hybrid Clean: Vita controller to replace the SBC (single board computing), Motorized Wafer Lift to replace the Pneumatic Lift and Fast PCV (pressure control valve) to replace the conventional PCV. Hybrid clean method proved to be able to increase the throughput by shorten the clean recipe time after each wafer and reduces the cost of consumables by reducing the amount of HCL (hydrogen chloride) clean gas to be used. Long term stability of Hybrid Clean was demonstrated during a 1000 wafer marathon.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128370327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Korabi, G. Graton, E. E. Adel, M. Ouladsine, J. Pinaton
{"title":"On the increase of the controllability matrix rank in non-threaded run-to-run control","authors":"T. Korabi, G. Graton, E. E. Adel, M. Ouladsine, J. Pinaton","doi":"10.1109/ASMC.2018.8373153","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373153","url":null,"abstract":"One of the levers for cycle time and cost reduction in the semiconductor industry is the use of all the available production tools as much as possible. In this paper, a modified Non-threaded Run-to-Run approach is proposed. This approach permits the control of the maximum possible number of equipment simultaneously. The idea is to model the entire system with all possible combinations (threads) in a novel state space representation (SSR) so that we can increase the rank of the controllability matrix. Due to its efficiency, especially with a SSR, a Kalman filter is used as an estimator for the Run-to-Run control purpose. The accuracy of the proposed method is tested using real data derived from the deposition area of STMicroelectronics foundry in Rousset.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128211157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Gregory M. Johnson, J. Nxumalo, Ankur Arya, Jeffrey Johnson, Qun Gao, Brian Greene
{"title":"Innovative use of FA techniques SCM and OBIRCH along with TCAD to resolve junction scaling issues at advanced technology nodes","authors":"Gregory M. Johnson, J. Nxumalo, Ankur Arya, Jeffrey Johnson, Qun Gao, Brian Greene","doi":"10.1109/ASMC.2018.8373206","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373206","url":null,"abstract":"A novel device engineering approach is presented that combines three analysis methods to examine leakage in SRAM-like test structures at advanced technology nodes. This system exploits the physics of laser-based failure analysis, combined with carrier profile measurements by SCM, and TCAD simulation for verification of process conditions responsible for leakage. This system accounts for process non-uniformity, finds nonvisual implant differences, thoroughly proves which variations actually cause electrical problems, and eliminates spurious findings. We also provide two unique findings where different types of local implant distribution problems were shown to cause either reverse bias leakage or early diode turn-on at low voltage forward bias.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123187463","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Advanced defect inspection techniques for NFET and PFET defectivity at 7nm gate poly removal process","authors":"Ian Tolle, Michael M. Daino","doi":"10.1109/ASMC.2018.8373197","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373197","url":null,"abstract":"During 7nm gate poly removal process, polysilicon is removed exposing both NFET and PFET fins in preparation for high-k gate oxide. If the polysilicon etch is too aggressive or the source and drain are not sufficiently protected, the etch can damage the active region and render the FET inoperative. Different materials are used in the active region for NFET and PFET that have different susceptibility to the polysilicon etch. To sufficiently monitor this defect, we must have good detection of damaged active regions on both PFET and NFET. However, PFET and NFET regions have very different optical noise characteristics due to varying levels of process uniformity. In addition, the distance between NFET and PFET has continued to shrink with the design rule, making evaluating each independently with optical inspection tools increasingly difficult. In this paper, we introduce new techniques to independently monitor both NFET and PFET defectivity, with improved performance over current methods.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132005703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
K. Wendt, Fabian Wilbers, J. Ruth, C. Lorant, F. Holsteyns, John N. Newby, G. Bast, V. Sundar
{"title":"Bare wafer analysis for wet cleaning efficiency — The impact of classification and sensitivity","authors":"K. Wendt, Fabian Wilbers, J. Ruth, C. Lorant, F. Holsteyns, John N. Newby, G. Bast, V. Sundar","doi":"10.1109/ASMC.2018.8373202","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373202","url":null,"abstract":"The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific \"killer defect\" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap1. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the wafer, it is required to track the individual position of each defect and to classify each of them as ‘cleanable’ or ‘non-cleanable’. When performing the post process particle inspection scan, this tracking will allow determining how many ‘cleanable’ defects could be removed during a wet cleaning process and will result in the ‘cleaning efficiency’ (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125743296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Keil, G. Schneider, Mathias Kuttig, A. Deutschländer, Arnold Lange, H. Heinrich
{"title":"Enhancing flexibility and robustness of semiconductor production by using autonomous modular services","authors":"S. Keil, G. Schneider, Mathias Kuttig, A. Deutschländer, Arnold Lange, H. Heinrich","doi":"10.1109/ASMC.2018.8373171","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373171","url":null,"abstract":"Increasing market requirements pose major challenges for semiconductor manufacturers. One major reason for this effect is for instance an increasing individualization of customer requirements, especially regarding the provision of more and more different functions on a single chip. A typical mature multi-product semiconductor manufacturer, which is on the \"More than Moore\" path within the logic business, produces several hundred different products in one fabrication facility, whereas the predictability of the production volumes per single product type decreases. Furthermore, the decreasing product life cycles lead to the necessity to continually introduce new products into the running production system [1].","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125006113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Determining a security roadmap for the microelectronics industry","authors":"J. Moyne, Supika Mashiro, David Gross","doi":"10.1109/ASMC.2018.8373213","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373213","url":null,"abstract":"The evolution of the microelectronics manufacturing industry is characterized by increased complexity, analysis, integration, distribution, data sharing and collaboration, all of which is enabled by the big data explosion. This evolution affords a number of opportunities in improved productivity and quality, and reduced cost, however it also brings with it a number of risks associated with maintaining security of data systems. The International Roadmap for Devices and System Factory Integration International Focus Team (IRDS FI IFT) determined that a security technology roadmap for the industry is needed to better understand the needs, challenges and potential solutions for security in the microelectronics industry and its supply chain. As a first step in providing this roadmap, the IFT conducted a security survey, soliciting input from users, suppliers and OEMs. Preliminary results indicate that data partitioning with IP protection is the number one topic of concern, with the need for industry-wide standards as the second most important topic. Further, the \"fear\" of security breach is considered to be a significant hindrance to Advanced Process Control efforts as well as use of cloud-based solutions. The IRDS FI IFT will endeavor to provide components of a security roadmap for the industry in the 2018 FI chapter, leveraging the output of the survey effort combined with follow-up discussions with users and consultations with experts.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125221475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shuren Hu, A. Stricker, K. McLean, Calvin Ma, S. Roy, Dean Percy, J. Cartier, D. Clark, R. van Roijen, Bart Green, K. Dezfulian, Louis Medina, J. Ferrario, Dave Riggs, K. Giewont
{"title":"Fully automated in-line optical test system: Advanced materials & photonics","authors":"Shuren Hu, A. Stricker, K. McLean, Calvin Ma, S. Roy, Dean Percy, J. Cartier, D. Clark, R. van Roijen, Bart Green, K. Dezfulian, Louis Medina, J. Ferrario, Dave Riggs, K. Giewont","doi":"10.1109/ASMC.2018.8373215","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373215","url":null,"abstract":"The development of a high throughput, accurate, and cost efficient inline optical test system is a key challenge to mass manufacturing of silicon photonics. For our Silicon Photonic technologies, we developed a fully automated wafer level optical test system for both, active and passive optical testing. The measured insertion loss of fiber grating couplers is repeatable within 1.1dB (3σ). A unique forward and reverse alternative test method is designed to extract photodetector responsivity.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125526034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}