Bare wafer analysis for wet cleaning efficiency — The impact of classification and sensitivity

The continued drive in the semiconductor industry for smaller, faster and cheaper integrated circuits has driven the industry to the 10nm technology node and beyond and ushered in a new era of high-performance 3-dimensional transistor structures. Consequently, the surface preparation is becoming more challenging especially particulate contamination will continue to be a concern at increasingly demanding levels. The Maly equation, with its use of a Poisson distribution, continues to be used to predict the allowable defect density of front surface particles based on yield (targeting 99.9%) for a specific "killer defect" size, i.e. the critical particle diameter for a specific technology node, which is now less than the MPU physical gate length. This results in equipment particle specifications and provides a more tangible Roadmap1. For cleaning processes, it is not only useful to determine how well the process is removing particulate contamination but also on how many defects are being introduced during this particular cleaning step. This insight is required to get a state on the cleanliness of the process and the related tool. For this calculation, a general pre and post defect difference of the processed wafer isn't any longer sufficient, but an improved personalized defect classification is mandatory. For example, during the pre process particle inspection scan of the wafer, it is required to track the individual position of each defect and to classify each of them as ‘cleanable’ or ‘non-cleanable’. When performing the post process particle inspection scan, this tracking will allow determining how many ‘cleanable’ defects could be removed during a wet cleaning process and will result in the ‘cleaning efficiency’ (CE) of a particular process executed on a particular tool. Furthermore, by considering the added defects as process induced defects (PID) the cleanliness of the process/tool can be determined.