优化BEOL R&C监控宏,以准确表示电路性能

Dewei Xu, R. Srivastava, Ushasree Katakamsetty, E. G. de la Garza, H. Kim, R. Augur, R. Fox
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引用次数: 0

摘要

R(线路电阻)和C(耦合电容)参数是量产的关键参数表甚至晶圆验收标准之一。过程工程师依靠R和C监控宏来调整过程以满足目标和控制规范。然而,R和C宏的性能和能力受到它们自己设计的很大影响。因此,正确设计R和C监视宏来表示产品中真正的R和C性能是至关重要的。在本研究中,我们展示了R和C监控宏的设计,以确保在底层金属层(CA/CB级别)和层上实现相同的金属密度。此外,期望的图案密度被设置为在感兴趣的领域(例如,SRAM,逻辑/模拟器件或其他有源电路)的主要模具的代表。因此,得到的金属线轮廓是一致的,相应的RC图代表了真实的RC性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization of BEOL R&C monitoring macros for accurate representation of circuit performance
R (line resistance) and C (coupling capacitance) parameters are among the critical parameter list or even wafer acceptance criteria in volume production. Process engineers rely on R and C monitoring macros to tune processes to meet targets and control specs. However, the performance and capability of the R and C macros are much impacted by their own design. Therefore, properly designed R and C monitoring macros to represent genuine R and C performance in the product are critical. In this study, we show R and C monitoring macros were designed to make sure the same metal density is implemented at the underlying metal layer (CA/CB level) and on-layer. Furthermore, the desired pattern density is desired to be set as representative of the prime die at areas of interest (for example, SRAM, logic/analog devices or other active circuits). Therefore, resulting metal line profiles are consistent and corresponding RC plots represent the genuine RC performance.
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