Impact of scribe line (kerf) defectivity on wafer yield

Abstract

Scribe line (also known as kerf or frame) is an area in a silicon wafer which is used to separate individual die at the end of wafer processing. This area also contains features which assist in the manufacturing process but are not present in a final product. Examples of such features include lithography alignment and overlay marks, thickness measurement pads and electric test macros. The overall design of scribe line features can be drastically different from the die layout. In the chemical mechanical polishing (CMP) process, regions of low pattern density have higher polishing rates compared to those of high pattern density, leading to overpolishing or "dishing". The scribe line, with intermittent regions of low and high pattern density, is naturally more prone to dishing, an issue which is exacerbated by thickness variation at the wafer edge. In this work, we present examples of how interaction between process variation and scribe line design can result in yield loss for the prime die.