2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)最新文献_第3页

Opportunities, challenges and use cases of digitization within the semiconductor industry 半导体行业数字化的机遇、挑战和用例

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373173

G. Schneider, S. Keil, G. Luhn

引用次数: 6

Minimally invasive servicing design 微创服务设计

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373219

Carlos Strocchia-rivera

引用次数: 0

Inline SEM imaging of buried defects using novel electron detection system: DI: Defect inspection and reduction 使用新型电子检测系统的埋藏缺陷的在线扫描电镜成像:DI:缺陷检测和减少

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373177

Abhinav Jain, J. G. Sheridan, F. Levitov, V. Aristov, Shay Yasharzade, Hoang Nguyen

引用次数: 1

A bi-criteria mixed integer linear programming model for load balancing and chemical saving in wafer cleaning processes: IE: Industrial engineering 用于晶圆清洗过程中负载平衡和化学节省的双标准混合整数线性规划模型:工业工程

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373188

S. Pazhani, T. Beeg, Kristopher Kowalczyk, Todd Dietrich

{"title":"A bi-criteria mixed integer linear programming model for load balancing and chemical saving in wafer cleaning processes: IE: Industrial engineering","authors":"S. Pazhani, T. Beeg, Kristopher Kowalczyk, Todd Dietrich","doi":"10.1109/ASMC.2018.8373188","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373188","url":null,"abstract":"Semiconductor manufacturing or wafer fabrication process involves multiple processing steps and is highly re-entrant, where a job may visit an equipment group more than once, at various stages of the product flow. Wafer cleaning process in semiconductor fabrication comprises multiple steps at various stages of the product flow to remove particles and oxidize organic contaminants, using different chemicals. This paper focusses on front-end of the line wafer cleaning steps. We consider J equipment groups which run I clean process steps and uses M different chemicals. Each step is qualified to run on a set of equipment groups and when recipes using different chemical run back to back on a tool-there is a chemical pre-dispense to clean and condition the nozzle. Given today's increasingly cost-conscious and competitive market, this study focuses on balancing loads on the equipment groups and minimize operating cost by reducing chemical pre-dispenses. We propose a bi-criteria mixed integer linear programming model to allocate daily demands to the equipment groups with the objectives of minimizing the maximum utilization and reducing chemical pre-dispenses. We also propose a priority based dispatching algorithm to translate the model output and implement in a dispatching system. Results show that the model reduces chemical pre-dispense resulting in significant cost saving, improved throughput due to cascading, and balanced utilization across the equipment groups.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121026118","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Rapid yield ramp using closed loop DFM and overlay process window qualification flow 采用闭环DFM和覆盖工艺窗口确认流程的快速产量坡道

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373192

Michael Wojtowecz, D. Ryan, K. Krishnamoorthy, Nabil Azad, Haizhou Yin, P. Babighian, U. Schroeder, M. Duggan, Panneerselvam Venkatachalam

{"title":"Rapid yield ramp using closed loop DFM and overlay process window qualification flow","authors":"Michael Wojtowecz, D. Ryan, K. Krishnamoorthy, Nabil Azad, Haizhou Yin, P. Babighian, U. Schroeder, M. Duggan, Panneerselvam Venkatachalam","doi":"10.1109/ASMC.2018.8373192","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373192","url":null,"abstract":"At advanced nodes (sub 28nm), it has become a major challenge to design and verify integrated circuits to achieve high yield. The complex interactions of design and manufacturing process need to be bridged by Design for Manufacturability (DFM) / Design for Yield (DFY). With further shrinking of process technology, the on-chip variation worsens for each technology node. As a result, traditional defect detection methodologies also become more challenging. Interlayer and/or overlay driven defects have begun to plague lithography patterning. Traditional Process Window Qualification (PWQ) (focus and dose modulation) alone may not define the true process window. Overlay has become an additional factor to aid in determining the complete process window. DFM brings manufacturing variability awareness into the design to address the yield limiting configurations using pattern matching and recommended rules. In this paper, we propose a closed loop DFM and Overlay Process Window (OPW) qualification flow to identify yield-limiting configurations and address them early in the product yield ramp for faster time-to-market (TTM).","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115228765","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Topography hotspot-aware process control metrology cell insertion: DFM: Design for manufacturability 地形热点感知过程控制测量单元插入:DFM:可制造性设计

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373199

M. R. Nishat, Ushasree Katakamsetty, V. Mehrotra, H. Landis, S. Nakagawa, Gazi Huda

引用次数: 3

Review-SEM image analysis with K-means algorithm: AM: Advanced metrology/DI: Defect inspection

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373221

S. Halder, D. Cerbu, M. Saib, P. Leray

引用次数: 3

Picosecond ultrasonics: Characterization of single crystal piezoelectric materials for advanced RF filters 皮秒超声:用于先进射频滤波器的单晶压电材料的表征

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373163

C. Hayden, J. Kwon, D. Kim, S. Gibb, R. Mair, J. Dai, X. Zeng, P. Mukundhan

引用次数: 1

Advanced industrial S/TEM automation and metrology: Boundary of precision 先进工业S/TEM自动化和计量:精度的边界

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373156

Haiyan Tan, Weihao Weng, R. Rai, Chris Kang, L. Dumas, I. Brooks, A. Katnani, Zhenxin Zhong, Chris Hakala, Yinggang Lu, J. Fretwell, Timothy A. Johnson

{"title":"Advanced industrial S/TEM automation and metrology: Boundary of precision","authors":"Haiyan Tan, Weihao Weng, R. Rai, Chris Kang, L. Dumas, I. Brooks, A. Katnani, Zhenxin Zhong, Chris Hakala, Yinggang Lu, J. Fretwell, Timothy A. Johnson","doi":"10.1109/ASMC.2018.8373156","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373156","url":null,"abstract":"Developments in the semiconductor industry are driving the need for new methods to characterize smaller 3D devices in a productive and reproducible way. The automation of sample preparation, TEM imaging, and offline CD metrology is able to provide sample information in the form of both images and quantitative data. In this article, we evaluate the TEM imaging automation workflow in order to optimize the experimental configuration towards better measurement precision and higher throughput. It is found that the top contributor to CD precision is the signal-to-noise ratio of the STEM image, which is determined by the electron flux. We investigated the top 5 most important experimental factors (probe current, image size, dwell time, Drift Corrected Frame integration, and image Field of View) and their interactions for a secondary contributor to CD precision. And we found that the combination of those factors play very minor role as soon as they contribute to the same electron flux. This learning guides us to configure our experiment parameters to optimize the trade-off between measurement precision and throughput.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130970314","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Shortest path CD measurement using contour extraction 利用轮廓提取进行最短路径CD测量

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373165

O. Patterson, Bart Seefeldt, Wan-Hsiang Liang, Haokun Hu, Joan Chen, yu-chi Su, Hsiang-Ting Yeh, Pengcheng Zhang

引用次数: 2