2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)最新文献_第2页

Asymmetric etching profile control during high aspect ratio Plasma etch 高纵横比等离子蚀刻时的不对称蚀刻轮廓控制

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373146

Zusing Yang, Li-Ian Wu, Sheng-Yuan Chang, Yuan-Chieh Chiu, Hong-Ji Lee, N. Lian, Tahone Yang, Kuang-Chao Chen, Chih-Yuan Lu, Hayato Watanabe, Yi-Sheng Cheng, Takao Arase, M. Mori

引用次数: 4

Study of titanium nitride underlayer properties and its influence on tungsten growth 氮化钛衬底性能及其对钨生长影响的研究

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373154

S. Pancharatnam, J. Wynne, G. Karve, A. Carr, B. Mendoza, L. White, G. Rodriguez, S. D. Vries, Wei Wang

引用次数: 0

Identifying cycle time factors and its relative impact on tools in semi-conductor fab using statistical inferences 利用统计推断确定周期时间因素及其对半导体晶圆厂工具的相对影响

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373190

Atirek Wribhu

引用次数: 1

An approach to fuzzy control of target function in consideration of equipment flexibility and workload in semiconductor photo lithography operations 半导体光刻作业中考虑设备灵活性和工作量的目标函数模糊控制方法

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373189

Kuan-Chang Chen, Bacon Tseng, Yu-Chih Wang, Yih-Yi Lee

引用次数: 0

Uncovering chemical quality improvements through a holistic approach to chemical quality management Contamination Free Manufacturing 通过全面的化学质量管理方法发现化学质量的改进

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373143

N. Colligan

引用次数: 1

Requirements for first-time-right response in advanced manufacturing 先进制造中对首次正确响应的要求

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373198

Boyd Finlay, Niels Rackwitz, Brian Conerney, Eric Warren, David Erdmann, K. Stoddard, A. Weber, T. Scanlon

{"title":"Requirements for first-time-right response in advanced manufacturing","authors":"Boyd Finlay, Niels Rackwitz, Brian Conerney, Eric Warren, David Erdmann, K. Stoddard, A. Weber, T. Scanlon","doi":"10.1109/ASMC.2018.8373198","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373198","url":null,"abstract":"The rapid pace of device scaling in recent years has outrun the ability of today's generation of semiconductor manufacturing equipment control systems to keep up. New device architectures and the materials and processes used to realize them create sources of variability that require better techniques for real-time sensing, filtering, detection, and response. This is not simply a question of faster data collection of the existing equipment variables. In many cases, the data needed to accurately determine the real-time process conditions are not even available in the equipment, so the traditional time-based techniques and endpoint detection methods for controlling recipe execution are not sufficient… rather, these advanced processes are effectively \"flying blind.\" GLOBALFOUNDRIES, a long-time leader in equipment automation and process control, has addressed these issues by integrating specialty sensors into the broader control environment, effectively closing this gap through a variety of advanced sensorization initiatives that supplement the capabilities of the equipment as delivered by the OEMs. The broad expectations regarding the capabilities of manufacturing equipment and the embedded control systems have recently been described in [1]. Specific examples of advanced sensorization use cases and a standards-based implementation approach have been described in [2]. Now that the measurement gaps for a number of key processes have thus been closed (see Tables 1 and 2), new application opportunities exist for leveraging this enhanced visibility into equipment and process behavior. In particular, the ability to achieve \"first-time-right response\" to a wide variety of process conditions is now a practical reality. This paper highlights a number of these applications possibilities enabled by \"unambiguous signals\" on the equipment, and touches on the integration solution used to present these signals seamlessly to the application environment.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"171 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131276807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Applying the Discrete Network Design Problem (DNDP) for designing AMHS layouts in semiconductor fabs 应用离散网络设计问题(DNDP)设计半导体晶圆厂的AMHS布局

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373158

Gerrit M. Kortus, Martin Däumler, T. Schmidt

{"title":"Applying the Discrete Network Design Problem (DNDP) for designing AMHS layouts in semiconductor fabs","authors":"Gerrit M. Kortus, Martin Däumler, T. Schmidt","doi":"10.1109/ASMC.2018.8373158","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373158","url":null,"abstract":"The Discrete Network Design Problem (DNDP) facilitates semi-automated AMHS layout generation in OHT systems. In order to increase fab productivity and mitigate waiting time, AMHS design often intends to reduce transportation time and to avoid congestion. During the time consuming and elaborate layout design process, simulation studies are frequently used for evaluating manually generated layouts. However, in this article an analytical approach is implemented, enabling semi-automated AMHS layout generation with no simulation needed. The applied DNDP is a bi-level mixed-integer optimization model, mostly used in road network design for determining optimal lane additions under consideration of dynamic routing and traffic equilibrium. In this article, the suitability of the DNDP for generating AMHS layouts is assessed. In addition, opportunities and limits of its application are discussed by means of an use case from semiconductor industry. Furthermore, additions to the formulation of the DNDP model are introduced to attain new functionality and ensure suitability to AMHS layout design. Due to its bilevel and non-convex structure, solving the DNDP in acceptable time is considered to be challenging. Thus, the application of two branch & bound algorithms and three heuristics (local search, tabu search and simulated annealing) for solving the DNDP in AMHS design is examined.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131903054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Brush cleaning effect on tugnsten voids defect in chemical mechanical polishing: CFM: Contamination free manufacturing 化学机械抛光中钨空洞缺陷的毛刷清洗效果:CFM:无污染制造

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373140

H. Kim, B. Egan, R. Solan, X. Shi, Ja-Hyung Han

引用次数: 2

Design systematic weak point discovery optimization 设计系统的弱点发现优化

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373204

Sonal Singh, Panneerselvam Venkatachalam, Julie Lee, Michael M. Daino, B. Saville, C. Lenox

{"title":"Design systematic weak point discovery optimization","authors":"Sonal Singh, Panneerselvam Venkatachalam, Julie Lee, Michael M. Daino, B. Saville, C. Lenox","doi":"10.1109/ASMC.2018.8373204","DOIUrl":"https://doi.org/10.1109/ASMC.2018.8373204","url":null,"abstract":"Design systematics have posed significant problems for the development of the latest technology nodes, specifically for logic with design rules of 28nm and below. The faster design systematics are identified, the faster the technology can mature into high volume manufacturing. For advanced design rules, the cost of these systematics increases exponentially with time and thus early detection yields high return on investment. In this paper, we report on a 2× increase in killer defect capture rate for PWQ (Process Window Qualification) inspections by revising the inspection layer. In addition, we found that we can also improve the signal-to-noise ratio (SNR) for single line opens (SLOs) for the actual inline process monitor at post-CMP. This experimentally measured SNR for SLOs was compared to a new computational tool to simulate the expected SNR of DOIs (defects of interest) from broadband plasma (BBP) inspection systems. The reported simulation tool was found to match experimental SNR as a function of the input physical defect model. As the physical defect model more closely matched the actual wafer, the closer the prediction was to the measured SNR. This new tool can aid in finding the best optical state for a given DOI and thus enable detection of the smallest design systematic faster than current methods.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116021325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A wafer map yield model based on deep learning for wafer productivity enhancement 基于深度学习的晶圆图良率模型

2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC) Pub Date : 2018-04-01 DOI: 10.1109/ASMC.2018.8373137

Sung-Ju Jang, Jee-Hyong Lee, Tae-Woo Kim, Jong-Seong Kim, Hyun-Jin Lee, Jong-Bae Lee

引用次数: 7