Sonal Singh, Panneerselvam Venkatachalam, Julie Lee, Michael M. Daino, B. Saville, C. Lenox
{"title":"Design systematic weak point discovery optimization","authors":"Sonal Singh, Panneerselvam Venkatachalam, Julie Lee, Michael M. Daino, B. Saville, C. Lenox","doi":"10.1109/ASMC.2018.8373204","DOIUrl":null,"url":null,"abstract":"Design systematics have posed significant problems for the development of the latest technology nodes, specifically for logic with design rules of 28nm and below. The faster design systematics are identified, the faster the technology can mature into high volume manufacturing. For advanced design rules, the cost of these systematics increases exponentially with time and thus early detection yields high return on investment. In this paper, we report on a 2× increase in killer defect capture rate for PWQ (Process Window Qualification) inspections by revising the inspection layer. In addition, we found that we can also improve the signal-to-noise ratio (SNR) for single line opens (SLOs) for the actual inline process monitor at post-CMP. This experimentally measured SNR for SLOs was compared to a new computational tool to simulate the expected SNR of DOIs (defects of interest) from broadband plasma (BBP) inspection systems. The reported simulation tool was found to match experimental SNR as a function of the input physical defect model. As the physical defect model more closely matched the actual wafer, the closer the prediction was to the measured SNR. This new tool can aid in finding the best optical state for a given DOI and thus enable detection of the smallest design systematic faster than current methods.","PeriodicalId":349004,"journal":{"name":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 29th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASMC.2018.8373204","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Design systematics have posed significant problems for the development of the latest technology nodes, specifically for logic with design rules of 28nm and below. The faster design systematics are identified, the faster the technology can mature into high volume manufacturing. For advanced design rules, the cost of these systematics increases exponentially with time and thus early detection yields high return on investment. In this paper, we report on a 2× increase in killer defect capture rate for PWQ (Process Window Qualification) inspections by revising the inspection layer. In addition, we found that we can also improve the signal-to-noise ratio (SNR) for single line opens (SLOs) for the actual inline process monitor at post-CMP. This experimentally measured SNR for SLOs was compared to a new computational tool to simulate the expected SNR of DOIs (defects of interest) from broadband plasma (BBP) inspection systems. The reported simulation tool was found to match experimental SNR as a function of the input physical defect model. As the physical defect model more closely matched the actual wafer, the closer the prediction was to the measured SNR. This new tool can aid in finding the best optical state for a given DOI and thus enable detection of the smallest design systematic faster than current methods.