Standardising utility savings

Abstract

As the semiconductor industry makes devices and integrated circuits (ICs) that are increasingly complex, a consequence has been that the number of processing steps is increasing, from 400 at 90nm to > 1000 in state-of-the-art designs [1], shown in Figure 1. Furthermore, despite many process steps becoming more utility (and especially electrical power) — efficient, the increasing number of times a wafer visits process chambers has resulted in the energy use per cm2 wafer area increasing, reversing the trend of previous years. Figure 2 illustrates this phenomenon, which is also exacerbated by the use of double and quadrupole patterning, 3D device stacking and the use of EUV in HVM (which reduces the number of process steps but is utility-intensive).