2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module 400G硅光子收发模块中四通道线性驱动芯片的晶圆级测试解决方案开发
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730947
Ye Wang, H. Ding, B. Blakely, Aidong Yan
{"title":"Wafer-Level Test Solution Development for a Quad-Channel Linear Driver Die in a 400G Silicon Photonics Transceiver Module","authors":"Ye Wang, H. Ding, B. Blakely, Aidong Yan","doi":"10.1109/ICMTS.2019.8730947","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730947","url":null,"abstract":"In this paper, we demonstrate a wafer-level sorting test solution developed for quad-channel linear driver to be used in a 400G silicon photonics transceiver module. In-house built tester-on-a-board (TOB) system was used to provide power and control signals to the device-under-test (DUT), as well as conduct parametric tests. RF switch matrix was implemented to support multi-channel RF tests up to 50GHz. This wafer sorting test solution covers contact tests, power consumption tests, single-ended and true-mode differential full S-parameter tests, output signal swing and total harmonic tests. This work enables wafer-level driver die sorting capability for next-generation 400G silicon photonics coherent transceiver module.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125195574","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
PbS Quantum Dot / ZnO Nanowires Hybrid Test Structures for Infrared Photodetector 红外探测器用PbS量子点/ ZnO纳米线混合测试结构
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730956
Haibin Wang, A. Higo, Y. Mita, T. Kubo, H. Segawa
{"title":"PbS Quantum Dot / ZnO Nanowires Hybrid Test Structures for Infrared Photodetector","authors":"Haibin Wang, A. Higo, Y. Mita, T. Kubo, H. Segawa","doi":"10.1109/ICMTS.2019.8730956","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730956","url":null,"abstract":"Aiming at developing infrared optoelectronic devices compatible with silicon-based large scale integration, we investigated performance of PbS colloidal quantum dot-silicon photodetectors using several different test structures. Silicon-based IR photo detector structures composed of PbS quantum dot / ZnO nanowire were investigated.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"103 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132251936","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Session 3: Novel Process Characterization 第三部分:新工艺表征
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/icmts.2019.8730950
{"title":"Session 3: Novel Process Characterization","authors":"","doi":"10.1109/icmts.2019.8730950","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730950","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123368079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch 齐纳二极管击穿电压失配的表征与建模
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730968
Man Yang, C. McAndrew, Lei Chao, K. Xia
{"title":"Characterization and Modeling of Zener Diode Breakdown Voltage Mismatch","authors":"Man Yang, C. McAndrew, Lei Chao, K. Xia","doi":"10.1109/ICMTS.2019.8730968","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730968","url":null,"abstract":"In this paper, we present test structures and procedures to characterize and model mismatch of the breakdown voltage of Zener diodes. Direct force-current/measure-voltage for breakdown is not sufficiently accurate for mismatch characterization, so we use an $I(V)$ sweep followed by cubic interpolation; the accuracy of this approach is verified using the Tuinhout DUT-1-2-1-2 methodology. To demonstrate our approach, we present measured and modeled breakdown voltage mismatch for 5 V Zener diodes in a 90 nm power BCD process.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121386496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fast Tera-Ohm Measurement Approach Using V93k AVI64 DC Scale Card 基于V93k AVI64直流刻度卡的快速太欧姆测量方法
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730977
Joem Stolle, Regis Poirier, Martin Froehle, Hermann Weindl, M. Naiman, V. Kriegerstein
{"title":"Fast Tera-Ohm Measurement Approach Using V93k AVI64 DC Scale Card","authors":"Joem Stolle, Regis Poirier, Martin Froehle, Hermann Weindl, M. Naiman, V. Kriegerstein","doi":"10.1109/ICMTS.2019.8730977","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730977","url":null,"abstract":"This paper describes a measurement approach for massive parallel testing enabling characterization of Mega-Ohm resistor and Giga-Ohm isolation structures for process characterization using low power test conditions with Advantest V93000 AVI64 equipment. Moreover, it exhibits the technique how to accomplish resistance readings up to single digit Tera-Ohms. Compared to a parametric benchmark tool, we are approx. 5x faster with sufficient accuracy and high repeatability. The new measurement methodology was applied for interconnect process characterization of an advanced CMOS technology.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132755346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Test structure to assess the useful extent of regular dummy devices around high-precision metal fringe capacitor arrays 测试结构,以评估高精度金属条纹电容器阵列周围的规则虚拟装置的有用程度
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730988
H. Tuinhout, I. Brunets, A. Z. Duijnhoven
{"title":"Test structure to assess the useful extent of regular dummy devices around high-precision metal fringe capacitor arrays","authors":"H. Tuinhout, I. Brunets, A. Z. Duijnhoven","doi":"10.1109/ICMTS.2019.8730988","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730988","url":null,"abstract":"This paper discusses metal fringe capacitor matching test structures to characterize the impact of layer density disturbances at the edges of capacitor arrays. It is demonstrated that a seemingly minor pattern density disturbance can significantly affect the systematic mismatch in capacitor arrays up to well over 5 μm away from the array edges.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"41 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126923684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies 一种优化直接光刻技术中模式近似的微赛道光谐振器测试结构
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730981
A. Higo, Tomoki Sawamura, M. Fujiwara, Etsuko Ota, Ayako Mizushima, E. Lebrasseur, T. Arakawa, Y. Mita
{"title":"A Micro Racetrack Optical Resonator Test Structure to Optimize Pattern Approximation in Direct Lithography Technologies","authors":"A. Higo, Tomoki Sawamura, M. Fujiwara, Etsuko Ota, Ayako Mizushima, E. Lebrasseur, T. Arakawa, Y. Mita","doi":"10.1109/ICMTS.2019.8730981","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730981","url":null,"abstract":"High-throughput electron beam (EB) lithography technologies such as variable shape beam (VSB) and character projection (CP) are drawing much interests to the industries due to the wafer scale exposure capability and reduced exposure time in the order of magnitude. However, the tradeoff relationship of the exposure quality according to the EB exposure pattern approximation methods has not yet been comprehensively studied. The study is essential for photonics because target patterns include curved shapes. We propose a test structure of silicon racetrack resonator to quantify the quality dependence. Three approximation techniques were tried such as octagon shape CP, tilted square CPs, and thin variable shape rectangles. Optical measurement clearly revealed quality differences between methods, which were impossible to be identified by classical metrological methods including Surface Probe Microscopy (SPM).","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129523908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Session 4: Resistive Materials 第四部分:电阻材料
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/icmts.2019.8730973
{"title":"Session 4: Resistive Materials","authors":"","doi":"10.1109/icmts.2019.8730973","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730973","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129918426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures 了解低温钝化退火对ZnO TFTs测试结构的影响
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730965
R. Rodriguez-Davila, P. Bolshakov, C. Young, M. Quevedo-López
{"title":"Understanding the Effects of Low-Temperature Passivation and Annealing on ZnO TFTs Test Structures","authors":"R. Rodriguez-Davila, P. Bolshakov, C. Young, M. Quevedo-López","doi":"10.1109/ICMTS.2019.8730965","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730965","url":null,"abstract":"Back-gate ZnO TFTs - with and without top-side passivation - were fabricated and electrically characterized. Passivation layers consisting of HfO<inf>2</inf>, Al<inf>2</inf>O<inf>3</inf>, and Parylene were introduced to study their impact on the TFT performance. Annealing was done to improve the electrical characteristics of passivated devices by neutralizing the initial charge introduced as a result of the low-temperature passivation. Low-temperature annealing combined with an Al<inf>2</inf>O<inf>3</inf>passivation layer demonstrates an I-V response comparable to ZnO TFTs without any passivation layer, indicating the viability of Al<inf>2</inf>O<inf>3</inf>as a good candidate for passivating ZnO TFTs.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124958815","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
[Copyright notice] (版权)
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/icmts.2019.8730917
{"title":"[Copyright notice]","authors":"","doi":"10.1109/icmts.2019.8730917","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730917","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134205388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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