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2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)最新文献

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In search of a hole inversion layer in $mathrm{Pd}/mathrm{MoO}_{x}/mathrm{Si}$ diodes through I- V characterization using dedicated ring-shaped test structures 在$ mathm {Pd}/ mathm {MoO}_{x}/ mathm {Si}$二极管中寻找空穴反转层，采用专用环形测试结构进行I- V表征
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-06-06 DOI: 10.1109/ICMTS.2019.8730920
G. Gupta, Shivakumar D. Tharnmaiah, R. Hueting, L. Nanver
{"title":"In search of a hole inversion layer in $mathrm{Pd}/mathrm{MoO}_{x}/mathrm{Si}$ diodes through I- V characterization using dedicated ring-shaped test structures","authors":"G. Gupta, Shivakumar D. Tharnmaiah, R. Hueting, L. Nanver","doi":"10.1109/ICMTS.2019.8730920","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730920","url":null,"abstract":"Palladium (Pd) capped molybdenum-oxide $(mathrm{MoO}_{x})$ thin films deposited bye-beam evaporation on p- and n-type silicon (Si) substrates were investigated employing dedicated ring-shaped test structures. The results show diode characteristics on n-type Si with a high rectification of $sim 10^{8}$ and a low leakage current of $sim pmb{10}^{-11}$ A and an ohmic contact on p-type Si, as expected from the reported high workfunction of $mathbf{MoO}_{x}$. Reports in the literature that an inversion layer of holes should be present at the $mathbf{MoO}_{x}/mathbf{n}$ -Si interface were investigated via various DC electrical measurements on lateral test structures, but no indication of any sianificant inversion was found.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123487760","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions 混合模态应力条件下SiGe HBTs的破坏机理分析
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730951
Mathieu Jaoul, D. Ney, D. Céli, C. Maneux, T. Zimmer
{"title":"Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions","authors":"Mathieu Jaoul, D. Ney, D. Céli, C. Maneux, T. Zimmer","doi":"10.1109/ICMTS.2019.8730951","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730951","url":null,"abstract":"This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(mathrm{L_{E}} > > mathrm{W}_{mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116818022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Electrical characterization of hot-wire assisted atomic layer deposited Tungsten films 热丝辅助原子层沉积钨薄膜的电学特性
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730954
Kees van der Zouw, A. Aarnink, J. Schmitz, A. Kovalgin
{"title":"Electrical characterization of hot-wire assisted atomic layer deposited Tungsten films","authors":"Kees van der Zouw, A. Aarnink, J. Schmitz, A. Kovalgin","doi":"10.1109/ICMTS.2019.8730954","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730954","url":null,"abstract":"In this work, we applied conventional Van der Pauw and circular transmission line method (CTLM) test structures to determine the sheet and contact resistance of ultra-thin (1-10 nm) tungsten films grown by Hot-Wire assisted Atomic Layer Deposition, as well as their temperature coefficient of resistance (TCR). We finally explored the field effect (FE) in these layers. From fundamental point of view, it is important to explore the impact of film thickness on film's electrical behavior, whereas practically this knowledge is crucial for the existing and foreseen applications.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"742 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133112108","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz 亚太赫兹下硅片上TRL校准测试结构设计引起的变化分析
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730962
C. Yadav, S. Frégonèse, M. Deng, M. Cabbia, M. De matos, Mathieu Jaoul, T. Zimmer
{"title":"Analysis of Test Structure Design Induced Variation in on Si On-wafer TRL Calibration in sub-THz","authors":"C. Yadav, S. Frégonèse, M. Deng, M. Cabbia, M. De matos, Mathieu Jaoul, T. Zimmer","doi":"10.1109/ICMTS.2019.8730962","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730962","url":null,"abstract":"In this paper, we present on-wafer S-parameter measurement of test structures designed and fabricated on silicon substrate for transistor de-embedding upto 220 GHz. Using two different types of reflects (open circuit and short circuit) in on-wafer thru-reflect-line (TRL) calibration, we show that in the on-wafer TRL, some of the error terms could be sensitive to the use of the reflect type and may not contain always exactly the same value with change in reflect type. Further, impact of reflect induced variations in error terms is demonstrated on the on-wafer TRL calibrated S-parameters of de-embedding structures. On basis of the on-wafer TRL calibrated S-parameters of de-embedding structures, we conclude that one type of reflect could suit more in the on-wafer TRL calibration for a de-embedding structure than another type.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132228812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges 靠近SOA边缘的多指SiGe hbt的物理、小信号和脉冲热阻抗特性
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730964
M. Couret, G. Fischer, S. Frégonèse, T. Zimmer, C. Maneux
{"title":"Physical, small-signal and pulsed thermal impedance characterization of multi-finger SiGe HBTs close to the SOA edges","authors":"M. Couret, G. Fischer, S. Frégonèse, T. Zimmer, C. Maneux","doi":"10.1109/ICMTS.2019.8730964","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730964","url":null,"abstract":"A thermal impedance model of single-finger and multi-finger SiGe heterojunction bipolar transistors (HBTs) is presented. The heat flow analysis through the device has to be considered in two diffusion parts: the front-end-of-line (FEOL) diffusion and the back-end-of-line (BEOL) diffusion. Therefore, this new thermal impedance model features multi-poles network which has been incorporated in HiCuM L2 compact model. The HiCuM compact model simulation results are compared with on-wafer low-frequency S-parameters measurements at room temperature highlighting the device frequency dependence of self-heating mechanism. The simulation results are also compared to pulse measurements to improve reliability analysis.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"254 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122543291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation 逻辑深度和切换速度对随机电报噪声引起的时延波动的影响
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730976
A. Islam, Ryota Shimizu, H. Onodera
{"title":"Effect of Logic Depth ad Switching Speed on Random Telegraph Noise Induced Delay Fluctuation","authors":"A. Islam, Ryota Shimizu, H. Onodera","doi":"10.1109/ICMTS.2019.8730976","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730976","url":null,"abstract":"We present measurement results of the effect of switching speed and logic depth on random telegraph noise (RTN) induced delay fluctuation using a test chip fabricated in a 65-nm Silicon-On- Thin-Buried-Oxide process. Measurement results reveal that the expected value of delay fluctuation decreases rapidly with the increase of logic depth. However, the delay fluctuation above 99th percentile is not strongly affected by logic depth. RTN-induced delay fluctuations are found to be not affected by the switching speed of logic gates. The measurement results provide useful insights into developing a statistical static timing analysis (SSTA) framework to asses the worst-case delay under the presence of RTN.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122283879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials 新一代存储材料统计分析电阻测量平台
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI: 10.1109/ICMTS.2019.8730955
T. Maeda, Y. Omura, A. Teramoto, R. Kuroda, T. Suwa, S. Sugawa
{"title":"Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials","authors":"T. Maeda, Y. Omura, A. Teramoto, R. Kuroda, T. Suwa, S. Sugawa","doi":"10.1109/ICMTS.2019.8730955","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730955","url":null,"abstract":"A newly developed resistance measurement platform is presented in this paper. The measurement platform consists of an array test circuit fabricated by a conventional 0.18 $mu mathrm{m}$ 1-Poly-Si 5-Metal layers CMOS technology, and a measurement target material formed on top of the 5M layer of the platform by an additional process. Using this platform, we can measure the resistance of various materials only by forming the measurement target layer and the top metal layer on the platform additionally. The resistance measurement operation was verified by measuring 234 poly-Si test resistor pre-formed by the poly-Si gate electrode layer in the array test circuit. Furthermore, 200 nm thick amorphous-Si layer was formed as a measurement target material on the platform and 490,700 cells were measured. The resistance measurement of 490,700 cells was conducted within 0.5 s with the resistance range of 500 $Omega- 10 mathrm{M}Omega$. We observed random telegraph noise (RTN) in some amorphous-Si cells. The developed platform is very useful for research and development of new memory materials, as well as for developing process, process equipment, and device structure to improve the reliability and performance of next generation memories.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128226607","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators 利用bti敏感和bti不敏感环振子提取无时间因素的bti诱导退化
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730967
Ryo Kishida, Takuya Asuke, J. Furuta, K. Kobayashil
{"title":"Extracting BTI-induced Degradation without Temporal Factors by Using BTI-Sensitive and BTI-Insensitive ring Oscillators","authors":"Ryo Kishida, Takuya Asuke, J. Furuta, K. Kobayashil","doi":"10.1109/ICMTS.2019.8730967","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730967","url":null,"abstract":"Measuring bias temperature instability (BTI) by ring oscillators (ROs) is frequently used. However, the performance of a semiconductor chip is fluctuated dynamically due to bias, temperature and etc. BTI-sensitive and -insensitive ROs are implemented in order to extract BTI-induced degradation without temporal fluctuation factors. A test chip including those ROs was fabricated in a 65 nm process. BTI-induced degradation without temporal fluctuation was successfully measured by subtracting results of BTI-insensitive ROs from those of BTI-sensitive ones. Performance degradation of NMOS and PMOS transistors mainly due to BTI increases along logarithmic and exponential functions, respectively.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129804428","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime 亚微米mosfet低频噪声从亚阈值到中等反转的体偏依赖性实验提取
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730953
C. Tanaka, K. Adachi, Atsushi Nakayama, Y. Iguchi, S. Yoshitomi
{"title":"Experimental Extraction of Body Bias Dependence of Low Frequency Noise in sub-micron MOSFETs from Subthreshold to Moderate Inversion Regime","authors":"C. Tanaka, K. Adachi, Atsushi Nakayama, Y. Iguchi, S. Yoshitomi","doi":"10.1109/ICMTS.2019.8730953","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730953","url":null,"abstract":"In this study, we investigate low frequency noise under the reverse body bias conditions from subthreshold to moderate inversion regime with 1/f noise measurement for small-area conventional nMOSFETs. The reverse body bias is not influenced on coulomb scattering process, even though the depletion capacitance was influenced by body bias. Furthermore, gate-to-bulk coupling was reduced flat-band fluctuations. These results suggest that reverse body bias is applicable to the low power and high signal-to-noise ratio for low current operation.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134350793","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise 利用纯白噪声确定MEMS振动能量采集器驻极体电荷势的方法
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730995
H. Mitsuya, H. Ashizawa, H. Homma, G. Hashiguchi, H. Toshiyoshi
{"title":"A Method to Determine the Electret Charge Potential of MEMS Vibrational Energy Harvester using Pure White Noise","authors":"H. Mitsuya, H. Ashizawa, H. Homma, G. Hashiguchi, H. Toshiyoshi","doi":"10.1109/ICMTS.2019.8730995","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730995","url":null,"abstract":"A high-throughput measurement method is developed to determine the electrical potential of electret embedded in a MEMS vibrational energy harvester. When a electret device is electrically excited with white noise voltage, the mechanical resonance disappears from the real-time FFT analysis when the superposed dc bias voltage compensates the electret potential, by which the magnitude of the electret potential is known.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123310542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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