Resistance Measurement Platform for Statistical Analysis of Next Generation Memory Materials

Abstract

A newly developed resistance measurement platform is presented in this paper. The measurement platform consists of an array test circuit fabricated by a conventional 0.18 $\mu \mathrm{m}$ 1-Poly-Si 5-Metal layers CMOS technology, and a measurement target material formed on top of the 5M layer of the platform by an additional process. Using this platform, we can measure the resistance of various materials only by forming the measurement target layer and the top metal layer on the platform additionally. The resistance measurement operation was verified by measuring 234 poly-Si test resistor pre-formed by the poly-Si gate electrode layer in the array test circuit. Furthermore, 200 nm thick amorphous-Si layer was formed as a measurement target material on the platform and 490,700 cells were measured. The resistance measurement of 490,700 cells was conducted within 0.5 s with the resistance range of 500 $\Omega- 10 \mathrm{M}\Omega$. We observed random telegraph noise (RTN) in some amorphous-Si cells. The developed platform is very useful for research and development of new memory materials, as well as for developing process, process equipment, and device structure to improve the reliability and performance of next generation memories.