2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)最新文献

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Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips 真正无源横杆存储阵列在短流量表征车辆测试芯片上的评估
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730984
C. Hess, T. Brożek, Hendrik Schneider, Yuan Yu, M. Lunenborg, Khim Hong Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. Weiland
{"title":"Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips","authors":"C. Hess, T. Brożek, Hendrik Schneider, Yuan Yu, M. Lunenborg, Khim Hong Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. Weiland","doi":"10.1109/ICMTS.2019.8730984","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730984","url":null,"abstract":"More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle® (CV®) Test Chips become beneficial for fast yield and endurance learning cycles. However, providing high observability of tail bits with ppm resolution requires access to more than just one bit cell per pad to be economically viable. Since, there are no FEOL switches available to address the bit cells we are evaluating truly Passive Crossbar Memory Arrays (PCMA) to significantly improve the bit per area ratio. Experimental results confirm successful memory operation based on fast parallel pulse testing. Design guidelines are presented to balance array size, signal to noise ratio, and test time.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122721257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
A compact model of I -V characteristic degradation for organic thin film transistors 有机薄膜晶体管I -V特性退化的紧凑模型
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730987
M. Saito, Michihiro Shintani, K. Kuribara, Y. Ogasahara, Takashi Sato
{"title":"A compact model of I -V characteristic degradation for organic thin film transistors","authors":"M. Saito, Michihiro Shintani, K. Kuribara, Y. Ogasahara, Takashi Sato","doi":"10.1109/ICMTS.2019.8730987","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730987","url":null,"abstract":"The lifetime of organic thin film transistors is known to be significantly shorter than that of silicon MOSFETs. It is hence important to predict their degradation at early design phase. This paper proposes a drain current model for simulating organic thin film transistors. The proposed model characterizes the degradation by the changes of the threshold voltage and carrier mobility. With the extracted parameters, the proposed model successfully reproduces temporal performance degradation of the fabricated devices. The experimental results also demonstrate that the proposed model achieves 38% better accuracy compared to the existing model.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116383223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Probing impact on pad moisture tightness: A challenge for pad size reduction 探测对衬垫防潮性的影响:减小衬垫尺寸的挑战
2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-01 DOI: 10.1109/ICMTS.2019.8730990
Matthias Vidal-Dhô, Q. Hubert, P. Gonon, Philippe Delorme, J. Jacquot, Maxime Marchetti, L. Beauvisage, J. Moragues, Pascale Potard, P. Fornara, Jean-Philippe Escales, Pascal Sallagoity, O. Pizzuto, Delphine Maury, J. Mirabel
{"title":"Probing impact on pad moisture tightness: A challenge for pad size reduction","authors":"Matthias Vidal-Dhô, Q. Hubert, P. Gonon, Philippe Delorme, J. Jacquot, Maxime Marchetti, L. Beauvisage, J. Moragues, Pascale Potard, P. Fornara, Jean-Philippe Escales, Pascal Sallagoity, O. Pizzuto, Delphine Maury, J. Mirabel","doi":"10.1109/ICMTS.2019.8730990","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730990","url":null,"abstract":"This paper underlines the damages induced by probing on narrow pads reliability of specifically designed test structures placed on dicing streets and indicates that probing during electrical test steps provokes detrimental cracks diving from the passivation through the BEOL layers providing a path for moisture ingress.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130571491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Invited Talk 2 特邀演讲2
P. Tuyls
{"title":"Invited Talk 2","authors":"P. Tuyls","doi":"10.1109/BLISS.2009.8","DOIUrl":"https://doi.org/10.1109/BLISS.2009.8","url":null,"abstract":"Hardware security is essential to the prevention of cloning, theft of service and tampering. Effective hardware security starts with secure key storage. The level of security provided by a key is dependent upon the effort an attacker needs to expend to compromise the key. The sophistication of the tools that are used to carry out such attacks has increased significantly over the years, compromising the protection of traditional key-storage approaches. A radically new approach is needed to counter this increased threat. Rather than trying harder to conceal the key in the hardware, a revolutionary approach has emerged in which the key is simply not stored. This new approach to hardware security relies on the unique electronic \"fingerprint\" inherent in every semiconductor device and is known as Hardware Intrinsic Security (HIS).","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-01-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131470083","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Invited Talk 1 特邀演讲1
T. Kean
{"title":"Invited Talk 1","authors":"T. Kean","doi":"10.1109/BLISS.2009.7","DOIUrl":"https://doi.org/10.1109/BLISS.2009.7","url":null,"abstract":"As tooling charges for ASICs increase inexorably over time, FPGAs become the technology of choice for a wider variety of applications. Today many designers are implementing secure systems using FPGAs and the shift towards FPGA can be expected to accelerate. Although FPGA chips are compelling from a cost and ease of use perspective they also have a unique set of security challenges, quite different from those faced on ASIC chips. Moreover, many of the established countermeasure techniques used on ASIC chips are not available to the FPGA designer working. This talk will consider the threat model for designers using FPGA. The two most important challenges are protecting the intellectual property in the user design against reverse engineering and cloning and, for designs which implement a security function, hardening the design against tampering and side channel attacks. Unfortunately, many of the most popular commercial FPGA families have not been designed with security in mind which limits the level of security that is achievable. This talk will consider the various technical mechanisms which have been proposed to address these challenges, outline their strengths and weaknesses and provide guidance on how to obtain reasonable levels of security in real world applications.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2009-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125363727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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