Evaluation of Truly Passive Crossbar Memory Arrays on Short Flow Characterization Vehicle Test Chips

C. Hess, T. Brożek, Hendrik Schneider, Yuan Yu, M. Lunenborg, Khim Hong Ng, D. Ciplickas, R. Vallishayee, C. Dolainsky, L. Weiland
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引用次数: 4

Abstract

More and more non volatile memory bit cell candidates are emerging which can be implemented between two metal layers in the BEOL process. Thus, short flow Characterization Vehicle® (CV®) Test Chips become beneficial for fast yield and endurance learning cycles. However, providing high observability of tail bits with ppm resolution requires access to more than just one bit cell per pad to be economically viable. Since, there are no FEOL switches available to address the bit cells we are evaluating truly Passive Crossbar Memory Arrays (PCMA) to significantly improve the bit per area ratio. Experimental results confirm successful memory operation based on fast parallel pulse testing. Design guidelines are presented to balance array size, signal to noise ratio, and test time.
真正无源横杆存储阵列在短流量表征车辆测试芯片上的评估
在BEOL工艺中,越来越多的非易失性存储位单元候选器件出现在两个金属层之间。因此,短流量表征车辆®(CV®)测试芯片有利于快速良率和耐久性学习周期。然而,要提供具有ppm分辨率的高可观察性尾钻头,需要在每个垫上安装不止一个位单元,才能在经济上可行。由于没有FEOL开关可用于处理位单元,我们正在评估真正的无源交叉棒存储器阵列(PCMA),以显着提高每面积比特比。实验结果证实了基于快速并行脉冲测试的存储操作是成功的。提出了平衡阵列大小、信噪比和测试时间的设计准则。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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