{"title":"Session 5: Power Device","authors":"","doi":"10.1109/icmts.2019.8730957","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730957","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124275112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Manabu Tomita, S. Mori, Y. Fukuzaki, K. Ogawa, S. Miyake, H. Ohnuma
{"title":"Extremely Low Voltage Operatable On-Chip- Monitor-Test Circuit for Plasma Induced Damage using High sensitivity Ring-VCO(Voltage Controlled Oscillator)","authors":"Manabu Tomita, S. Mori, Y. Fukuzaki, K. Ogawa, S. Miyake, H. Ohnuma","doi":"10.1109/ICMTS.2019.8730985","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730985","url":null,"abstract":"We developed an on-chip-monitor-test circuit that measures Vth fluctuation caused by plasma induced damage (PID) during wafer process with using a novel ring voltage controlled oscillator (Ring- VCO) at low Vdd operation condition. The circuit can be easily implemented to conventional design and applied to product test. We have demonstrated that the circuit fabricated by 28nm process can monitor Vth fluctuation due to PID with operating voltage at 0.5V, which can be used for low power IoT products by 28nm CMOS technology and beyond.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116692670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Two-transistor Voltage-Measurement-Based Test Structure for Fast Extraction of MOS Mismatch Design Parameters","authors":"J. P. M. Brito, S. Bampi","doi":"10.1109/ICMTS.2019.8730918","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730918","url":null,"abstract":"This paper proposes a new test structure and a measurement method for measuring MOS transistors mismatches. The structure is based on the combination of two stacked MOS transistors and the measurement methodology relies on two single DC voltage measurements. The method allows to extract separately $sigma(triangle V_{TH})$ and $sigma(Deltabeta/beta)$ and enables fast extraction of design MOS mismatch parameters such as $A_{V_{TH}}$ and $A_{beta}$ with less than 2% error. The simple data post-processing algorithm results in an increase of $pmb{30mathrm{x}}$ in the measurement speed with data correlation coefficient not less than 0.94 $(R^{2}geq pmb{0.94})$. Rapid address decoding and bias configuration have been used in order to select each device in a two-dimensional (2D) DUT matrix of FETs. The experimental data presented herein for analysis is taken from measurements in a prototype fabricated in 65nm CMOS bulk process.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116589861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Blank page]","authors":"","doi":"10.1109/icmts.2019.8730958","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730958","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131445197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Blank page]","authors":"","doi":"10.1109/icmts.2019.8730919","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730919","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128266149","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Proposed one-dimensional passive array test circuit for parallel kelvin measurement with efficient area use","authors":"Matthew Rerecich, C. Young","doi":"10.1109/ICMTS.2019.8730948","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730948","url":null,"abstract":"A test structure and measurement method are proposed that permits measurement of several resistors in parallel using a kelvin method with only two independent pads per device. This technique allows rapid measurement of several different resistors with efficient area usage and a simple and adaptable circuit architecture.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131613120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"[Blank page]","authors":"","doi":"10.1109/icmts.2019.8730972","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730972","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"330 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133982564","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hiroki Tsukamoto, Michihiro Shintani, Takashi Sato
{"title":"A study on statistical parameter modeling of power MOSFET model by principal component analysis","authors":"Hiroki Tsukamoto, Michihiro Shintani, Takashi Sato","doi":"10.1109/ICMTS.2019.8730946","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730946","url":null,"abstract":"In this paper, a set of dominant model parameters, which largely contributes characteristic variation of power MOSFETs, has been studied on the basis of statistical parameter extraction. Through the numerical analysis upon measured drain currents of a SiC power MOSFET, we demonstrate that the fluctuation of the current characteristics can be represented by a few random variables. In our example, threshold voltage and current scaling factor are identified particularly important to approximate the fluctuation of the current characteristics.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114193361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On-Chip Threshold Voltage Variability Detector Targeting Supply of Ring Oscillator for Characterizing Local Device Mismatch","authors":"Poorvi Jain, Bishnu Das","doi":"10.1109/ICMTS.2019.8730952","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730952","url":null,"abstract":"In this work, an all-digital on-chip threshold voltage variability detector is proposed to detect the local random threshold voltage variation from an array of device under test (DUTs). The use of single ring oscillator (RO) results in the compact structure of the proposed design. Any mismatch in the DUT is reflected as the change in the voltage of the sense node which is connected to the supply voltage of the RO. The difference of RO periods due to change in voltage level from $V_{DD}$ to $(V_{DD}-V_{TH})$ at the sense node actually represents the impact of threshold voltage of a DUT. The mismatch in threshold voltage of the DUTs can be modeled exponentially from the RO period difference. The difference nature of estimation technique enables to mitigate the impact of local supply voltage variation and error due to systematic variations in the path of the RO. The potency of the proposed technique is demonstrated using measurement results from a fabricated test chip designed in a $pmb{0.13}mu m$ process technology node. Measurement results from a test chip indicate that the test structure can estimate local random threshold voltage variations and is also useful in improving the yield as well as in process optimization.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124482039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}