混合模态应力条件下SiGe HBTs的破坏机理分析

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS) Pub Date : 2019-03-18 DOI:10.1109/ICMTS.2019.8730951

Mathieu Jaoul, D. Ney, D. Céli, C. Maneux, T. Zimmer

{"title":"混合模态应力条件下SiGe HBTs的破坏机理分析","authors":"Mathieu Jaoul, D. Ney, D. Céli, C. Maneux, T. Zimmer","doi":"10.1109/ICMTS.2019.8730951","DOIUrl":null,"url":null,"abstract":"This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(\\mathrm{L_{E}} > > \\mathrm{W}_{\\mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions\",\"authors\":\"Mathieu Jaoul, D. Ney, D. Céli, C. Maneux, T. Zimmer\",\"doi\":\"10.1109/ICMTS.2019.8730951\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(\\\\mathrm{L_{E}} > > \\\\mathrm{W}_{\\\\mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.\",\"PeriodicalId\":333915,\"journal\":{\"name\":\"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2019-03-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICMTS.2019.8730951\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICMTS.2019.8730951","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

本文研究了先进SiGe hts中热载流子的降解问题。这种破坏机制是在混合模式应力条件下观察到的。通过不同发射极宽度WE的二维晶体管$(\mathrm{L_{E}} > > \mathrm{W}_{\mathrm{E}})$的直流测量来检测其物理位置。通过TCAD模拟来确定其物理来源和位置。该方法允许识别位于发射器-基间隔器界面的退化机制的起源。它是基于在混合模式(MM)应力条件下对器件施加10,000 s应力后测量的直流特性的可扩展分析。本研究证实了SiGe HBTs的MM降解机制。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Analysis of a failure mechanism occurring in SiGe HBTs under mixed-mode stress conditions

This paper presents an investigation of hot carrier degradation in advanced SiGe HBTs. This failure mechanism is observed under mixed mode stress conditions. Its physical location is examined through DC measurements from 2D transistors $(\mathrm{L_{E}} > > \mathrm{W}_{\mathrm{E}})$ with different emitter width WE. TCAD simulations were performed to confirm its physical origin and location. The methodology permits to identify the origin of the degradation mechanism located at the emitter-base spacer interface. It is based on the scalable analysis of the DC characteristics measured after stressing the devices during 10 000s under mixed mode (MM) stress conditions. This study confirms the mechanism responsible of the MM degradation for SiGe HBTs.

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来源期刊

2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)

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