2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)最新文献

{"title":"High-k Oxides on Hydrogenated-Diamond for Metal-Oxide-Semiconductor Field-Effect Transistors [Invited]","authors":"Y. Koide","doi":"10.1109/ICMTS.2019.8730974","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730974","url":null,"abstract":"Thanks to its excellent intrinsic properties, diamond is promising for applications of high-power electronic devices, ultraviolet detectors, biosensors, high-temperature tolerant gas sensors, etc. Here, an overview of high-k oxides on hydrogenated-diamond (H-diamond) for metal-oxide-semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) is demonstrated. Fabrication routines for the H-diamond MOS capacitors and MOSFETs, band configurations of oxide/H-diamond heterointerfaces, and electrical properties of the MOS and MOSFETs are summarized and discussed. High-k oxide insulators are deposited using atomic layer deposition (ALD) and sputtering deposition (SD) techniques. Electrical properties of the H-diamond MOS capacitors with high-k oxides of $mathbf{ALD}-mathbf{Al}_{2}mathbf{O}_{3}, mathbf{ALD}-mathbf{HfO}_{2},mathbf{ALD}-mathbf{HfO}2/mathbf{ALD}-mathbf{Al_{2}O}_{3}$ multilayer, $mathbf{SD}-mathbf{HfO}_{2}/mathbf{ALD}-mathbf{HfO}_{2}$ bilayer, $mathbf{SD-TiO_{2}/ALD-Al_{2}mathrm{O}_{3}}$ bilayer, and ALD $mathbf{TiO_{2}/ALD-Al_{2}O_{3}}$ bilayer are discussed. Analyses for capacitance-voltage characteristics of them show that there are low fixed and trapped charge densities for the $mathbf{ALD}-mathbf{Al}_{2}mathbf{O}_{3}/mathbf{H}$ -diamond and $mathrm{SD}-mathbf{HfO}_{2}/mathbf{ALD}-mathbf{HfO}_{2}/mathbf{H}-$ diamond MOS capacitors. The k value of 27.2 for the $mathbf{ALD-TiO_{2}/ALD-Al_{2}}mathbf{O}_{3}$ bilayer is larger than those of the other oxide insulators. Drain-source current versus voltage curves show distinct pitch-off and p-type channel characteristics for the $mathbf{ALD}-mathbf{Al_{2}mathrm{O}_{3}}/mathbf{H}$ -diamond, SD- $mathbf{EfO}_{2}/mathbf{ALD}-mathbf{HfO}_{2}/mathbf{H}$ -diamon d, and $mathbf{ALD}-mathbf{TiO}_{2}/mathbf{ALD}- mathbf{A}1_{2}mathbf{O}_{3}/mathbf{H}$ -diamond MOSFETs. Understanding of fabrication routines and electrical properties for the high-k oxide/H-diamond MOS electronic devices is meaningful for the fabrication of high-performance H-diamond MOS capacitor and MOSFETs.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117122097","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"[Blank page]","authors":"","doi":"10.1109/icmts.2019.8730983","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730983","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124669993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session 7: Measurement Technique","authors":"","doi":"10.1109/icmts.2019.8730923","DOIUrl":"https://doi.org/10.1109/icmts.2019.8730923","url":null,"abstract":"","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"41 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131609618","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Comparison of MOSFET Threshold Voltage Extraction Methods with Temperature Variation","authors":"Yu-Hsing Cheng","doi":"10.1109/ICMTS.2019.8730978","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730978","url":null,"abstract":"Threshold voltage is a fundamental parameter for MOSFET device and technology characterization. Multiple threshold voltage extraction methods are compared in this paper with experimental data over a wide temperature range from −40°C to 150°C for 5V and 1.8V NMOS devices in a 180 nm BCD process. Consistent results are found among two linear extrapolation methods from the drain current versus gate voltage transfer characteristics and transition method for MOSFETs biased in the linear region. The difference in temperature coefficients of extracted threshold voltages from different methods are compared and the different trends of scaled drain currents at extracted threshold voltages over temperature are analyzed to reveal the underestimation of threshold voltage temperature coefficients in gm/Id methods.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123744858","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"A Study of Power Supply Stability in Ring Oscillator Structures","authors":"Brad Smith, D. Hall, B. Verzi, Daniel W. Pechonis","doi":"10.1109/ICMTS.2019.8730980","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730980","url":null,"abstract":"The stability of the supply rails while testing wafer-level ring oscillator structures has been studied. The power and ground supplies were observed to be disturbed by a switching output signal, a result of the tester hardware being unable to respond fast enough to maintain stable voltages. It was shown that using stronger test hardware to provide 0 V improved the stability of the ground voltage. It was further shown that the addition of discrete capacitors between the power supplies improved the stability of the supply voltage. The areas under curves in the supply voltage waveforms were used as quality metrics to quantify the charge involved in the disruption and to evaluate different solutions. Samples from six technologies built in three factories all showed the same issues and responded to the hardware changes, demonstrating that the issue was not sensitive to Si technology.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129912714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests","authors":"C. Sia","doi":"10.1109/ICMTS.2019.8730921","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730921","url":null,"abstract":"The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved. Semiconductor packaging companies must perform wafer acceptance tests to qualify their copper pillar micro-bumping process. Probecards and single DC probes are unable to address the measurement challenges and flexibilities needed for micro-bump wafer acceptance tests, which measure the micro-bump resistance and the wafer surface leakage currents in a single setup. In this paper, consistent and repeatable test results are obtained in a fully automatic manner using custom DC positioners with theta-X planarizing capability and true Kelvin probes for micro-bump resistance measurements as well as standard DC probes for wafer surface leakage measurements.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127646580","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Test Structures for Characterising the Silver Chlorination Process During Integrated Ag/AgCl Reference Electrode Fabrication","authors":"C. Dunare, J. Marland, E. Blair, A. Tsiamis, F. Moorel, J. Terry, Anthony J. Walton, Stewart Smith","doi":"10.1109/ICMTS.2019.8730966","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730966","url":null,"abstract":"Robust and repeatable processes are required to fabricate reference electrodes for micro-scale integrated electrochemical sensors. One method for this is to produce a “silver/silver chloride” (Ag/Agel) electrode through chemical chlorination of a thin film silver layer. This paper presents test structures, which can electrically characterise the process to aid process development and in-line control of the chlorination process.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116622185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Modeling and Test Structures for Accurate Current Sensing in Vertical Power FETs","authors":"M. Chu, T. Harjono, K. Joardar, V. Krishnamurthy","doi":"10.1109/ICMTS.2019.8730949","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730949","url":null,"abstract":"A new approach using a combination of analytical models, Spice simulations, and test structures is reported that allows for a comprehensive treatment of 3-dimensional (3D) distributed effects in vertical power FETs. This method leads to higher accuracy in current sensing as well as more cost effective design cycles.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"236 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132362928","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Optimization of 3ω Method for Phase-Change Materials Thermal Conductivity Measurement at High Temperature","authors":"A. Serra, G. Bourgeois, M. Cyrille, J. Cluzel, J. Garrione, G. Navarro, E. Nowak","doi":"10.1109/ICMTS.2019.8730993","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730993","url":null,"abstract":"Thermal conductivity (kth) of Ge-rich Ge-Sb-Te phase-change material (GGST) is here investigated at temperatures up to $400 ^{circ}mathrm{C}$ through “3ω method”. We present the engineering of the test vehicle, with the optimization of the metal-based heater to achieve a reliable measurement even at high temperature. Finally, we compare the results from four different approaches, showing which method is more accurate for the kth evaluation in phase-change materials.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134451773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Continuity assessment for supercritical-fluids-deposited (SCFD) Cu film as electroplating seed layer","authors":"Naoto Usamil, Etsuko Ota, A. Higo, T. Momose, Y. Mita","doi":"10.1109/ICMTS.2019.8730945","DOIUrl":"https://doi.org/10.1109/ICMTS.2019.8730945","url":null,"abstract":"We evaluated supercritical fluid deposition (SCFD) copper thin films compatibility as a seed layer of electroplating processes. SCFD is an attractive technology for conformal metal coating on walls of high-aspect-ratio micro / nano structures (HARMS / HARNS), including trenches and holes. Therefore, it has a great potential for an electroplating seed layer. To utilize SCFD films as seed layers, we assessed the electrical and topological continuity of the SCFD films. The electrical measurements efficiently identified the suitability of various SCFD films for the electroplating process, which could not be achieved by microscope observation. The results have been cross-validated by atomic force microscopy.","PeriodicalId":333915,"journal":{"name":"2019 IEEE 32nd International Conference on Microelectronic Test Structures (ICMTS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122487421","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}