Characterization of Micro-Bumps for 3DIC Wafer Acceptance Tests

The strong market needs to embed multiple functionalities from different semiconductor processing technologies into a single system continue to drive demands for more advanced 3DIC packaging technologies. Dimensions of copper pillar micro-bumps are consistently reduced in every new technology node to facilitate the 3D stacking of multiple dies so that overall system performance can be improved. Semiconductor packaging companies must perform wafer acceptance tests to qualify their copper pillar micro-bumping process. Probecards and single DC probes are unable to address the measurement challenges and flexibilities needed for micro-bump wafer acceptance tests, which measure the micro-bump resistance and the wafer surface leakage currents in a single setup. In this paper, consistent and repeatable test results are obtained in a fully automatic manner using custom DC positioners with theta-X planarizing capability and true Kelvin probes for micro-bump resistance measurements as well as standard DC probes for wafer surface leakage measurements.