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Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A 使用Verilog-A的节奏virtuoso纳米磁逻辑建模和仿真
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324722
G. Ziemys, Andrew Giebfried, M. Becherer, I. Eichwald, D. Schmitt-Landsiedel, S. B. Gamm
{"title":"Modelling and simulation of nanomagnetic logic with cadence virtuoso using Verilog-A","authors":"G. Ziemys, Andrew Giebfried, M. Becherer, I. Eichwald, D. Schmitt-Landsiedel, S. B. Gamm","doi":"10.1109/ESSDERC.2015.7324722","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324722","url":null,"abstract":"This paper presents an efficient compact model of a single nanomagnet implemented in Verilog-A. A single magnet is the key element of nanomagnetic logic systems. Two field coupled nanomagnets act as a magnetic inverter. To verify the model, a circuit consisting of five such single magnets in a loop is simulated and the results are compared to an experiment on an fabricated inverter chain. To reproduce the variations in a manufacturing process the Monte Carlo simulation method is applied and the magnetization direction of the last magnet in a chain is evaluated for one hundred clocking cycles. The results are compared to the experimental data.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126417571","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering 基于寄生工程的单片集成三维CMOS逻辑电路版图设计新方法
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324763
C. Tanaka, K. Ikeda, M. Saitoh
{"title":"New layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering","authors":"C. Tanaka, K. Ikeda, M. Saitoh","doi":"10.1109/ESSDERC.2015.7324763","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324763","url":null,"abstract":"We propose a new layout design methodology for monolithically integrated 3D CMOS logic circuits based on parasitics engineering. In order to understand the impact of parasitics in monolithic 3D-stacked CMOS circuits, careful analysis of intra- and inter- layer parasitic capacitances were performed by using physics-based RC extractor for realistic 3D structure. As a result, we found that separation of power-supply (Vdd) and ground-line (GND) layer from logic elements is a key to reduce the parasitic capacitance thanks to be suppressed electrical coupling between stacked layers. By comparative evaluation among possible 3D layer configurations, we revealed that the best configuration is Vdd and GND layer sandwiched between nFET and pFET logic layers. Performance benchmarking by energy consumption-switching delay demonstrated that a 40% improvement of energy-delay product at Vdd = 0.5 V can be achieved by using a proposed layout methodology.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123463165","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model 应变对纳米线mosfet迁移率的影响:几何效应和压阻模型
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324752
J. Pelloux-Prayer, M. Cassé, F. Triozon, S. Barraud, Y. Niquet, J. Rouviere, O. Faynot, G. Reimbold
{"title":"Strain effect on mobility in nanowire MOSFETs down to 10nm width: Geometrical effects and piezoresistive model","authors":"J. Pelloux-Prayer, M. Cassé, F. Triozon, S. Barraud, Y. Niquet, J. Rouviere, O. Faynot, G. Reimbold","doi":"10.1109/ESSDERC.2015.7324752","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324752","url":null,"abstract":"The effect of strain on carrier mobility in triple gate FDSOI nanowires is experimentally investigated through piezoresistance measurements. We propose an empirical model based on simple assumptions that allows fitting the piezoresistive coefficients as well as the carrier mobility for various device geometries. We highlight an enhanced strain effect for Trigate nanowires with channel height below 11nm.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125040742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Electric performance of AlGaN/GaN heterojunction devices: A full-quantum study AlGaN/GaN异质结器件的电性能:全量子研究
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324778
L. Lucci, Jean-Charles Barb, M. Pala
{"title":"Electric performance of AlGaN/GaN heterojunction devices: A full-quantum study","authors":"L. Lucci, Jean-Charles Barb, M. Pala","doi":"10.1109/ESSDERC.2015.7324778","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324778","url":null,"abstract":"In this contribution a full-quantum simulation of the electron transport in the two-dimensional electron gas (2DEG) of a AlGaN/GaN heterostructure is carried out using the non-equilibrium Green function (NEGF) approach. Even if electrical and mechanical properties of a AlGaN/GaN heterojunction are now well understood, a host of techniques like thinning of layers as in gate recess, use of advance materials like high-k dielectrics, introduction of back-barriers or channel interfaces, are considerably intricating the physical modeling of the heterojunction and precise simulations that correctly take into account for physical effects at the nano-scale are deemed necessary. In this study the quantum-mechanical effects in the electron transport layer properties are accounted for both in the quantization and in the transport direction. First, we focus in particular to a comparative study of the threshold voltage formation. We then we address the gate scaling, identifying the channel length at which short-channel-effects may be nonnegligible any more.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"145 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123304900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Charge trapping in gate-drain access region of AlGaN/GaN MIS-HEMTs after drain stress 漏应力作用下AlGaN/GaN mishemts栅极-漏极通道的电荷捕获
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324712
S. Jauss, S. Schwaiger, W. Daves, S. Noll, O. Ambacher
{"title":"Charge trapping in gate-drain access region of AlGaN/GaN MIS-HEMTs after drain stress","authors":"S. Jauss, S. Schwaiger, W. Daves, S. Noll, O. Ambacher","doi":"10.1109/ESSDERC.2015.7324712","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324712","url":null,"abstract":"In this paper we investigate the drain stress behavior and charge trapping phenomena of GaN-based high electron mobility transistors (HEMTs). We fabricated GaN-on-Si MIS-HEMTs with different dielectric stacks in the gate and gate drain access region and performed interface characterization and stress measurements for slow traps analysis. Our results show a high dependency of the on-resistance increase on interfaces in the gate-drain access region. The dielectric interfaces near the channel play a significant role for long term high voltage stress and regeneration of the device.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131931310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Investigations of vapor phase deposited transition metal dichalcogenide films for future electronic applications 气相沉积过渡金属二硫化物薄膜在未来电子应用中的研究
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324705
T. Hallam, Hye-Young Kim, M. O'Brien, Riley Gatensby, N. McEvoy, G. Duesberg
{"title":"Investigations of vapor phase deposited transition metal dichalcogenide films for future electronic applications","authors":"T. Hallam, Hye-Young Kim, M. O'Brien, Riley Gatensby, N. McEvoy, G. Duesberg","doi":"10.1109/ESSDERC.2015.7324705","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324705","url":null,"abstract":"In this work we present investigations on ultrathin and monolayered transition metal dichalcogenides (TMDs). These recently have raised much interest for their applications in electronics. TMDs can be n- and p-type semiconductors and some of them undergo a change in band structure when thinned to a monolayer. In particular, with the TMD MoS2, a number of devices such as transistors, photodiodes, LEDs and chemical sensors have been demonstrated. In this report we focus on devices derived from MoS2 that is grown by methods that can be employed for the large scale synthesis.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130225150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Threshold voltage and on-current Variability related to interface traps spatial distribution 阈值电压和电流变异性与界面陷阱空间分布有关
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324756
V. Velayudhan, J. Martín-Martínez, M. Porti, Carlos Couso, R. Rodríguez, M. Nafría, X. Aymerich, C. Márquez, F. Gámiz
{"title":"Threshold voltage and on-current Variability related to interface traps spatial distribution","authors":"V. Velayudhan, J. Martín-Martínez, M. Porti, Carlos Couso, R. Rodríguez, M. Nafría, X. Aymerich, C. Márquez, F. Gámiz","doi":"10.1109/ESSDERC.2015.7324756","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324756","url":null,"abstract":"Interface traps can be a source of variability in MOSFETs, leading to statistically distributed electrical characteristics of devices. This work discusses, from 3D TCAD simulations, the effect of the spatial distribution of interface traps on the variability of the threshold voltage and the on-current of MOSFETs. The results suggest that threshold voltage is mainly influenced by the trap distribution along the channel of the device, whereas on-current is also influenced by the alignment of the traps along the device width. Implications for device electrical symmetry are discussed.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132232661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Engineering of a TiNAl2O3(Hf, Al)O2Ta2O5Hf RRAM cell for fast operation at low current TiNAl2O3(Hf, Al)O2Ta2O5Hf RRAM电池的设计
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324764
C. Y. Chen, L. Goux, A. Fantini, R. Degraeve, A. Redolfi, G. Groeseneken, M. Jurczak
{"title":"Engineering of a TiNAl2O3(Hf, Al)O2Ta2O5Hf RRAM cell for fast operation at low current","authors":"C. Y. Chen, L. Goux, A. Fantini, R. Degraeve, A. Redolfi, G. Groeseneken, M. Jurczak","doi":"10.1109/ESSDERC.2015.7324764","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324764","url":null,"abstract":"In this paper we engineer a TiNAl<sub>2</sub>O<sub>3</sub>(Hf, Al)O<sub>2</sub>Ta<sub>2</sub>O<sub>5</sub>Hf Oxide Resistive Random Access Memory (OxRRAM) device for fast switching at low operation current without sacrificing the retention and endurance properties. The integrated 40nm × 40nm cell switches at 10μA using write pulses shorter than 100ns (resp. 1us) for RESET (resp. SET) and with amplitude <;2V. Using these conditions in a verify algorithm, a resistive window of x10 is reliably obtained, decreasing the write speed by more than 1 decade compared to state-of-the-art OxRRAM stacks.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132927573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution 利用各向异性湿法蚀刻在TMAH溶液中制备高性能AlGaN/GaN FinFET
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324730
D. Son, Y. Jo, Ryun-Hwi Kim, Chan Heo, J. Seo, Jin Su Kim, I. Kang, S. Cristoloveanu, Jung-Hee Lee
{"title":"Fabrication of high performance AlGaN/GaN FinFET by utilizing anisotropic wet etching in TMAH solution","authors":"D. Son, Y. Jo, Ryun-Hwi Kim, Chan Heo, J. Seo, Jin Su Kim, I. Kang, S. Cristoloveanu, Jung-Hee Lee","doi":"10.1109/ESSDERC.2015.7324730","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324730","url":null,"abstract":"AlGaN/GaN-based fin-shaped field-effect transistors (FinFETs) with very steep sidewall and various fin-widths (Wfin) have been fabricated by utilizing electron-beam lithography and additional anisotropic sidewall wet etch in tetramethyl ammonium hydroxide (TMAH) solution. The device with Wfin of 180 nm exhibits normally-on performance with threshold voltage of -3.5 V and extremely broad transconductance (gm) characteristic ranging from -2 to ~ 3 V at VD = 5 V which is essential for high linearity device performance. This broad gm characteristic is because the current from the side-wall MOS channel becomes comparable to that from the two-dimensional electron gas (2DEG) channel and hence significantly contributes to the total device current. On the other hand, devices with smaller Wfin = 50 and 100 nm exhibit normally-off performance with positive threshold voltage of 2.0 and 0.6 V, respectively, and less broad gm characteristics because the current from the side-wall MOS channel dominates the total device current.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127784984","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Concept for a security aware automatic fare collection system using HF/UHF dual band RFID transponders 使用HF/UHF双频射频识别转发器的安全自动收费系统的概念
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324748
Lukas Zoscher, J. Grosinger, Raphael Spreitzer, U. Muehlmann, Hannes Gross, W. Bösch
{"title":"Concept for a security aware automatic fare collection system using HF/UHF dual band RFID transponders","authors":"Lukas Zoscher, J. Grosinger, Raphael Spreitzer, U. Muehlmann, Hannes Gross, W. Bösch","doi":"10.1109/ESSDERC.2015.7324748","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324748","url":null,"abstract":"Established automatic fare collection (AFC) solutions for public transport systems that use proximity HF radio frequency identification (RFID) smart cards are lacking a convenient method to determine the alighting point of a passenger. This paper considers an AFC system based on passive HF/UHF dual band RFID transponders. A UHF RFID link is envisaged for remote passenger detection. The paper discusses the general system architecture of the proposed AFC system. Furthermore, an appropriate security layer is introduced that also covers privacy concerns related to the remote passenger detection. We identify that the RF performance of the UHF RFID sub-system of a HF/UHF dual band RFID transponder is critical for the reliability of the remote passenger detection. The architecture and implementation challenges of a corresponding future HF/UHF dual band transponder IC are discussed.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117344692","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
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