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2015 45th European Solid State Device Research Conference (ESSDERC)最新文献

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Analysis of InAs-Si heterojunction double-gate tunnel FETs with vertical tunneling paths 垂直隧穿路径的InAs-Si异质结双栅隧道场效应管分析
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324774
H. Carrillo-Nuñez, M. Luisier, A. Schenk
{"title":"Analysis of InAs-Si heterojunction double-gate tunnel FETs with vertical tunneling paths","authors":"H. Carrillo-Nuñez, M. Luisier, A. Schenk","doi":"10.1109/ESSDERC.2015.7324774","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324774","url":null,"abstract":"InAs-Si double-gate TFETs exploiting the two-dimensional (2D) density-of-state (DOS) switch are studied. A full-band and atomistic quantum transport simulator based on the sp3d5s* tight-binding model is used to solve the quantum transport problem taking into account both lateral and vertical band-to-band tunneling paths. TFETs with only vertical tunneling components are also investigated. Our findings suggest that InAs-Si 2D-2D TFETs might offer a device solution with both steep sub-thermal sub-threshold swing (SS) and high ON-current. In the best case of an extremely thin InAs-Si 2D-2D TFET the minimal swing reaches SS = 12mV/dec and the ON-current 241 A/m.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132312261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array 基于硅纳米线阵列的亚15nm栅极全能垂直场效应晶体管
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324750
G. Larrieu, Y. Guerfi, X. L. Han, N. Clément
{"title":"Vertical field effect transistor with sub-15nm gate-all-around on Si nanowire array","authors":"G. Larrieu, Y. Guerfi, X. L. Han, N. Clément","doi":"10.1109/ESSDERC.2015.7324750","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324750","url":null,"abstract":"A vertical MOS architecture implemented on Si nanowire (NW) array with a scaled Gate-All-Around (14nm) and symmetrical diffusive S/D contacts is presented with noteworthy demonstrations both in processing (layer engineering at nanoscale), in electrical properties (high electrostatic control, low defect level, multi-Vt platform) in the fabrication of CMOS inverters and in the perspective of ultimate scaling.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127723116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
UTBB FDSOI: Evolution and opportunities UTBB FDSOI:进化和机遇
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324717
T. Skotnicki, S. Monfray
{"title":"UTBB FDSOI: Evolution and opportunities","authors":"T. Skotnicki, S. Monfray","doi":"10.1109/ESSDERC.2015.7324717","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324717","url":null,"abstract":"As today's 28nm FDSOI technology is at the industrialization level, this paper aims to summarize the key advantages allowed by the thin BOX (Buried Oxide) of the FDSOI, through the technology evolution but also through new opportunities, wider than logic applications and extending the possibility offered by the technology.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122009123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
Improving the resistive switching uniformity of forming-free TiO2−x based devices by embedded Pt nanocrystals 通过嵌入Pt纳米晶体改善无形成TiO2−x基器件的电阻开关均匀性
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324767
P. Bousoulas, D. Sakellaropoulos, J. Giannopoulos, D. Tsoukalas
{"title":"Improving the resistive switching uniformity of forming-free TiO2−x based devices by embedded Pt nanocrystals","authors":"P. Bousoulas, D. Sakellaropoulos, J. Giannopoulos, D. Tsoukalas","doi":"10.1109/ESSDERC.2015.7324767","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324767","url":null,"abstract":"The resistive switching characteristics of TiN/Ti/TiO2-x/Au devices containing Pt nanocrystals with different diameters, were systematically investigated. We demonstrate that comparing the reference with the Pt nanocrystals embedded devices, important enhancement of switching characteristics is obtained, in terms of uniformity and enlarged switching ratio. Our results indicate that the switching characteristics of TiO2-x device are very strongly related with the control of conductive filaments' growth within the dielectric layer, which stems from the local enhancement of the electric field in the vicinity of nanocrystals. This effect in conjunction with the room temperature fabrication process and the forming free nature of the thin films is considered as an optimization route of resistive random access memory design.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126696752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Energy harvesting with on-chip solar cells and integrated DC/DC converter 能量收集与片上太阳能电池和集成的DC/DC转换器
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324733
C. Steffan, Philipp Greiner, B. Deutschmann, Carolin Kollegger, G. Holweg
{"title":"Energy harvesting with on-chip solar cells and integrated DC/DC converter","authors":"C. Steffan, Philipp Greiner, B. Deutschmann, Carolin Kollegger, G. Holweg","doi":"10.1109/ESSDERC.2015.7324733","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324733","url":null,"abstract":"In this paper an energy-autonomous fully integrated photovoltaic driven harvesting solution for wireless sensor node applications is proposed. Photo diodes in parallel connection are used as on-chip micro solar cells. In order to provide the highest efficiency for ambient harvesting purposes, the n-well to p-substrate junction, which gives a negative voltage related to the p-substrate, is used. A test chip in a 130 nm CMOS technology, with different solar-cell configurations was designed and investigated. Numerous performance measurements were carried out in order to compare the on-chip solar cells. The achieved fill factor is 78% at 25 klux and 42°C. A charge pump circuit including a flying capacitor driver which allows the usage of the generated negative voltage is also presented.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"221 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134345117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
A new physics-based compact model for Bilayer Graphene Field-Effect Transistors 一种新的基于物理的双层石墨烯场效应晶体管紧凑模型
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324743
Jorgue Daniel Aguirre Morales, S. Frégonèse, C. Mukherjee, C. Maneux, T. Zimmer
{"title":"A new physics-based compact model for Bilayer Graphene Field-Effect Transistors","authors":"Jorgue Daniel Aguirre Morales, S. Frégonèse, C. Mukherjee, C. Maneux, T. Zimmer","doi":"10.1109/ESSDERC.2015.7324743","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324743","url":null,"abstract":"In this paper, a new compact model for Dual-Gate Bilayer Graphene Field-Effect Transistors is presented. The model uses a physics-based density of states (DOS) to compute the current and the charge. Moreover, the effect of back-gate biasing on the flatband voltage, residual carrier density and access resistances is implemented in the model for accurate description of the drain current. The developed large-signal compact model has been implemented in Verilog-A and its accuracy has been evaluated by comparison with measurements from the literature.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115461036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
5G wireless communication beyond 2020 2020年以后的5G无线通信
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324699
J. Hansryd
{"title":"5G wireless communication beyond 2020","authors":"J. Hansryd","doi":"10.1109/ESSDERC.2015.7324699","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324699","url":null,"abstract":"In the last twenty years we have seen a revolution comparable to the industrialization. We have gone from voice, to data, to mobile broadband to a situation where half of the two-year olds in Sweden use internet. We have changed how we are creating and sharing knowledge, how we interact with family and friends, how we work and how we do business. We have seen traditional industries transform... music, media ... and how more and more industries are rapidly digitalizing and mobilizing - realizing the need for good ICT solutions where mobility is becoming not only an opportunity, but a necessity.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116416161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Compact modeling of DG-Tunnel FET for Verilog-A implementation 用于Verilog-A实现的dg隧道场效应管的紧凑建模
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324708
A. Biswas, L. D. Michielis, A. Bazigos, A. Ionescu
{"title":"Compact modeling of DG-Tunnel FET for Verilog-A implementation","authors":"A. Biswas, L. D. Michielis, A. Bazigos, A. Ionescu","doi":"10.1109/ESSDERC.2015.7324708","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324708","url":null,"abstract":"In this work, a compact model based on an analytical closed form solution of the 1D Poisson's equation for a double-gate Tunnel FET is derived. Furthermore, the current levels are estimated by implementing an algorithm based on the Kane's band-to-band tunneling model. A good agreement with numerical simulations for varying device parameters is demonstrated and the advantages and limitations of the modeling approach are investigated and discussed. The model is implemented in a Verilog-A based circuit simulator and basic circuit blocks like an inverter, a 2-bit half adder and a 15 stage ring oscillator are simulated to demonstrate the capabilities of the model. The switching energy of a Tunnel FET based circuit block is studied with Vdd scaling revealing interesting aspects of Tunnel FET circuit behavior.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127227914","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Thin-film SOI PIN-diode leakage current dependence on back-gate-potential and HCI traps 薄膜SOI pin二极管泄漏电流对后门电位和HCI陷阱的依赖
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324771
Andrei Schmidt, S. Dreiner, H. Vogt, U. Paschen
{"title":"Thin-film SOI PIN-diode leakage current dependence on back-gate-potential and HCI traps","authors":"Andrei Schmidt, S. Dreiner, H. Vogt, U. Paschen","doi":"10.1109/ESSDERC.2015.7324771","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324771","url":null,"abstract":"We investigated the leakage current of thin film silicon-on-insulator (SOI) pin-diodes in dependence of the back-gate potential and hot carrier induced traps. Leakage current of virgin and hot-carrier stressed diodes was measured at distinct back-gate potentials. TCAD simulations were used to determine the mechanisms of leakage current generation at specific back-gate potentials. Traps were introduced to study the impact of hot-carrier stress on the leakage current. Location, polarity and density of traps were considered. For a virgin device tunneling is predominant in inversion and accumulation. In full depletion surface generation dominates the leakage behavior. Surface and oxide traps shift the leakage current and alter its mechanism with increasing density, i.e. stress time. In inversion trap generation dominates at the top SOI interface. In depletion top and bottom interface traps are generated.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127547981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Plasmonic and electronic device integrated circuits and their characteristics 等离子体和电子器件集成电路及其特性
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324724
M. Fukuda, H. Sakai, T. Mano, Y. Kimura, M. Ota, M. Fukuhara, T. Aihara, Y. Ishii, T. Ishiyama
{"title":"Plasmonic and electronic device integrated circuits and their characteristics","authors":"M. Fukuda, H. Sakai, T. Mano, Y. Kimura, M. Ota, M. Fukuhara, T. Aihara, Y. Ishii, T. Ishiyama","doi":"10.1109/ESSDERC.2015.7324724","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324724","url":null,"abstract":"This paper presents a type of plasmonic circuit that is monolithically integrated with electronic devices on a silicon substrate and discusses the concept behind this circuit. Surface plasmon waveguides and detectors are integrated with metal-oxide-semiconductor field-effect transistors (MOSFETs) on the substrate. In the circuits, surface plasmon signals are generated by light at a wavelength at which silicon is transparent, and propagate along the waveguide before being converted into electrical signals by the detector. These electrical signals drive the MOSFETs during both dc and ac operation. The measured performances of these devices indicate that the surface plasmons propagate on the metal surface at the speed of light and drive the electronic devices without any absorption in silicon.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125402712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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