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Technology and design of GaN power devices GaN功率器件的技术与设计
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324714
P. Moens, A. Banerjee, P. Coppens, A. Constant, P. Vanmeerbeek, Z. Li, F. Declercq, L. Schepper, H. Vleeschouwer, C. Liu, B. Padmanabhan, W. Jeon, J. Guo, A. Salih, M. Tack
{"title":"Technology and design of GaN power devices","authors":"P. Moens, A. Banerjee, P. Coppens, A. Constant, P. Vanmeerbeek, Z. Li, F. Declercq, L. Schepper, H. Vleeschouwer, C. Liu, B. Padmanabhan, W. Jeon, J. Guo, A. Salih, M. Tack","doi":"10.1109/ESSDERC.2015.7324714","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324714","url":null,"abstract":"This paper reports on the technology and design aspects of an industrial DHEMT process for 650V rated GaN-on-Si power devices, using an in-situ MOCVD grown SiN as surface passivation and gate dielectric, with low interface state density and excellent TDDB. Optimization of the GaN epi stack results in very low off-state leakage (<;10nA/mm). Due to the reduction of buffer trapping, low dynamic Ron (<;10%) is obtained, both at room temperature and at high temperature.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115308812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR 基于MASTAR的三极管-绝缘子MOSFET宽高比优化
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324759
G. Hiblot, Q. Rafhay, L. Gaben, G. Ghibaudo, F. Boeuf
{"title":"Optimization of Trigate-On-Insulator MOSFET aspect ratio with MASTAR","authors":"G. Hiblot, Q. Rafhay, L. Gaben, G. Ghibaudo, F. Boeuf","doi":"10.1109/ESSDERC.2015.7324759","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324759","url":null,"abstract":"In this work, the optimum design of Trigate-on-Insulator MOSFET devices is investigated with the MASTAR platform, focusing on the channel aspect ratio. First, the MAS-TAR Trigate model is described, and new components are validated with TCAD simulations. Using the verilog-A implementation of this model, SPICE simulations of inverter chains are later performed to analyze the device performance, employing different power reduction techniques. Finally, the variability issue is addressed with Monte-Carlo simulations of 6T SRAM cells.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115504229","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Experimental analysis of planar edge terminations for high voltage 4H-SiC devices 高压4H-SiC器件平面边端实验分析
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324715
V. Soler, M. Berthou, A. Mihaila, J. Montserrat, P. Godignon, J. Rebollo, J. Millán
{"title":"Experimental analysis of planar edge terminations for high voltage 4H-SiC devices","authors":"V. Soler, M. Berthou, A. Mihaila, J. Montserrat, P. Godignon, J. Rebollo, J. Millán","doi":"10.1109/ESSDERC.2015.7324715","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324715","url":null,"abstract":"Several edge termination structures for high voltage 4H-SiC devices compatible with a planar MOSFET fabrication process are analyzed in this paper. The edge terminations' efficiency has been analyzed on PiN diodes with breakdown voltage capabilities ranging from 2-5kV fabricated with full MOSFET process. Different edge terminations consisting in JTEs and FGRs, and a combination of JTEs and FGRs have been implemented. Experimental results show a good efficiency of the implemented edge terminations. It is shown that FGRs could be an effective cost solution for high voltage devices. Moreover, the edge termination combining JTE and FGRs shows a better tolerance of the JTE dose for maximizing the breakdown voltage, and the same edge termination design allows obtaining a good efficiency for both 2 and 5kV PiN diodes.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114154468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
FinFET versus UTBB SOI — A RF perspective FinFET与UTBB SOI - A射频透视
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324719
J. Raskin
{"title":"FinFET versus UTBB SOI — A RF perspective","authors":"J. Raskin","doi":"10.1109/ESSDERC.2015.7324719","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324719","url":null,"abstract":"FinFET and Ultra Thin Body and BOX (UTBB) Silicon-on-Insulator (SOI) MOSFETs are the most promising advanced devices to fulfill the International Technology Roadmap for Semiconductors (ITRS) requirements. Both devices have been intensively studied these last years. Most of the reported data concern their digital performance. In this paper, their analog/RF behavior is described and compared. Both show pretty similar characteristics in terms of transconductance, Early voltage, voltage gain, self-heating issue but UTBB outperforms FinFET in terms of cutoff frequencies thanks to their relatively lower fringing parasitic capacitances.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114846590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
On the fly characterization of charge trapping phenomena at GaN/dielectric and GaN/AlGaN/dielectric interfaces using impedance measurements 基于阻抗测量的氮化镓/电介质和氮化镓/氮化镓/电介质界面电荷俘获现象的动态表征
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324716
R. Stradiotto, G. Pobegen, C. Ostermaier, T. Grasser
{"title":"On the fly characterization of charge trapping phenomena at GaN/dielectric and GaN/AlGaN/dielectric interfaces using impedance measurements","authors":"R. Stradiotto, G. Pobegen, C. Ostermaier, T. Grasser","doi":"10.1109/ESSDERC.2015.7324716","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324716","url":null,"abstract":"Charge trapping phenomena at interfaces of GaN-based semiconductors with a dielectric are one of the major concerns in modern MIS-HEMT technologies. Fundamental questions about the nature and the behavior of interface defects must still be answered. We address these questions by investigating devices with and without an AlGaN layer at the the interface with the dielectric, using MIS capacitor test structures. We consider different methodologies to perform and analyze impedance measurements and the results are compared and discussed. Special attention is paid to the uncertainties and limitations inherent to different techniques, as well as the challenges due to the composite structure of GaN/AlGaN devices. We introduce an on the fly technique which allows the extraction of the device drift during stress. This enables us to suggest a lower and upper boundary for the amount of device degradation. The experimental results indicate the presence of similar defects at GaN and AlGaN surfaces, which therefore appear to be intrinsic to the III-N material.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"198 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124436749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Back-gate effects and detailed characterization of junctionless transistor 无结晶体管的后门效应及详细表征
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324769
M. Parihar, Fanyu Liu, C. Navarro, S. Barraud, M. Bawedin, I. Ionica, A. Kranti, S. Cristoloveanu
{"title":"Back-gate effects and detailed characterization of junctionless transistor","authors":"M. Parihar, Fanyu Liu, C. Navarro, S. Barraud, M. Bawedin, I. Ionica, A. Kranti, S. Cristoloveanu","doi":"10.1109/ESSDERC.2015.7324769","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324769","url":null,"abstract":"The work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125740595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Implementation of ARM® Cores in FinFET technolgies ARM®内核在FinFET技术中的实现
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324718
Y. Laplanche
{"title":"Implementation of ARM® Cores in FinFET technolgies","authors":"Y. Laplanche","doi":"10.1109/ESSDERC.2015.7324718","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324718","url":null,"abstract":"We present the main process steps in FinFET technologies in the 14/16nm nodes that shape the designer's work and discuss their implications at the Physical IP level. The document is particularly focused on the impact of the devices and the back-end-of-line on standard cell architectures.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131534147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Ge/III-V MOS device technologies for low power integrated systems 低功耗集成系统的Ge/III-V MOS器件技术
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324704
S. Takagi, M. Takenaka
{"title":"Ge/III-V MOS device technologies for low power integrated systems","authors":"S. Takagi, M. Takenaka","doi":"10.1109/ESSDERC.2015.7324704","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324704","url":null,"abstract":"CMOS utilizing high mobility Ge/III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport properties. In addition, Tunneling-FETs (TFETs) using Ge/III-V materials are regarded as one of the most important steep slope devices for the ultra-low power applications. In this paper, we address the device and process technologies of Ge/III-V MOSFETs and TFETs on the Si CMOS platform. The channel formation, source/drain (S/D) formation and gate stack engineering are introduced for satisfying the device requirements. The plasma post oxidation to form GeOx interfacial layers is a key gate stack technology for Ge CMOS. Also, direct wafer bonding of ultrathin body quantum well III-V-OI channels, combined with Tri-gate structures, realizes high performance III-V nMOSFETs on Si with threshold voltage tunability. We also demonstrate planar-type Ge/strained SOI and InGaAs TFETs. The defect-less p+/n source junction formation with steep impurity profiles is a key for high performance TFET operation.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127418141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Contact resistance extraction methods for CNTFETs cntfet接触电阻提取方法
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324773
A. Pacheco-Sánchez, S. Mothes, M. Claus, M. Schröter
{"title":"Contact resistance extraction methods for CNTFETs","authors":"A. Pacheco-Sánchez, S. Mothes, M. Claus, M. Schröter","doi":"10.1109/ESSDERC.2015.7324773","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324773","url":null,"abstract":"Three different methods for the extraction of the contact resistance based on both the well-known transfer length method (TLM) and two variants of the Y-function method have been applied to simulation and experimental data of CNTFETs and the results have been compared. While for TLM special CNT test structures are mandatory, standard electrical device characteristics are sufficient for the Y-function methods. The methods have been applied to CNTFETs with low and high channel resistance. It turned out that the standard Y-function method fails to deliver the correct contact resistance in case of a relatively high channel resistance compared to the contact resistances. A physical validation is also given for the application of these methods based on traditional Si MOSFET theory to quasi-ballistic CNTFETs.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130028126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Strain engineering of single-layer MoS2 单层MoS2的应变工程
2015 45th European Solid State Device Research Conference (ESSDERC) Pub Date : 2015-11-12 DOI: 10.1109/ESSDERC.2015.7324777
Manouchehr Hosseini, M. Elahi, E. Soleimani, M. Pourfath, D. Esseni
{"title":"Strain engineering of single-layer MoS2","authors":"Manouchehr Hosseini, M. Elahi, E. Soleimani, M. Pourfath, D. Esseni","doi":"10.1109/ESSDERC.2015.7324777","DOIUrl":"https://doi.org/10.1109/ESSDERC.2015.7324777","url":null,"abstract":"In this work the effect of biaxial and uniaxial strain on the mobility of single-layer MoS2 at room temperatures is comprehensively studied. Scattering from intrinsic phonon modes, remote phonon and charged impurities are considered along with static screening. Ab-initio simulations are utilized to investigate the strain induced effects on the electronic bandstructure and the linearized Boltzmann transport equation is used to evaluate the low-field mobility under various strain conditions. The results indicate that the mobility increases with tensile biaxial and tensile uniaxial strain along the armchair direction. Under compressive strain, however, the mobility exhibits a nonmonotonic behavior when the strain magnitude is varied. In particular, with a relatively small compressive strain of 1% the mobility is reduced by about a factor of two compared to the unstrained condition, but with a larger compressive strain the mobility partly recovers such a degradation.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"96 Suppl 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123367544","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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