Experimental analysis of planar edge terminations for high voltage 4H-SiC devices

Abstract

Several edge termination structures for high voltage 4H-SiC devices compatible with a planar MOSFET fabrication process are analyzed in this paper. The edge terminations' efficiency has been analyzed on PiN diodes with breakdown voltage capabilities ranging from 2-5kV fabricated with full MOSFET process. Different edge terminations consisting in JTEs and FGRs, and a combination of JTEs and FGRs have been implemented. Experimental results show a good efficiency of the implemented edge terminations. It is shown that FGRs could be an effective cost solution for high voltage devices. Moreover, the edge termination combining JTE and FGRs shows a better tolerance of the JTE dose for maximizing the breakdown voltage, and the same edge termination design allows obtaining a good efficiency for both 2 and 5kV PiN diodes.