M. Parihar, Fanyu Liu, C. Navarro, S. Barraud, M. Bawedin, I. Ionica, A. Kranti, S. Cristoloveanu
{"title":"无结晶体管的后门效应及详细表征","authors":"M. Parihar, Fanyu Liu, C. Navarro, S. Barraud, M. Bawedin, I. Ionica, A. Kranti, S. Cristoloveanu","doi":"10.1109/ESSDERC.2015.7324769","DOIUrl":null,"url":null,"abstract":"The work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Back-gate effects and detailed characterization of junctionless transistor\",\"authors\":\"M. Parihar, Fanyu Liu, C. Navarro, S. Barraud, M. Bawedin, I. Ionica, A. Kranti, S. Cristoloveanu\",\"doi\":\"10.1109/ESSDERC.2015.7324769\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation.\",\"PeriodicalId\":332857,\"journal\":{\"name\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-11-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 45th European Solid State Device Research Conference (ESSDERC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2015.7324769\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 45th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2015.7324769","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Back-gate effects and detailed characterization of junctionless transistor
The work addresses effect of inter-gate coupling on back-channel characteristics of planar accumulation-mode junctionless (JL) MOSFETs, fabricated with advanced FDSOI technology. A systematic methodology to extract and discriminate the contributions of bulk and accumulation-mode mobility has been developed. Front-gate voltage strongly controls the properties of back channel in ultra-thin heavily doped JL devices. It has been demonstrated that both volume and accumulation-mode mobilities increase when the front surface is in accumulation.