{"title":"Implementation of ARM® Cores in FinFET technolgies","authors":"Y. Laplanche","doi":"10.1109/ESSDERC.2015.7324718","DOIUrl":null,"url":null,"abstract":"We present the main process steps in FinFET technologies in the 14/16nm nodes that shape the designer's work and discuss their implications at the Physical IP level. The document is particularly focused on the impact of the devices and the back-end-of-line on standard cell architectures.","PeriodicalId":332857,"journal":{"name":"2015 45th European Solid State Device Research Conference (ESSDERC)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 45th European Solid State Device Research Conference (ESSDERC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2015.7324718","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
We present the main process steps in FinFET technologies in the 14/16nm nodes that shape the designer's work and discuss their implications at the Physical IP level. The document is particularly focused on the impact of the devices and the back-end-of-line on standard cell architectures.